Pavel Makovský: Geopolitical aspects of transport interconnections development in the Southern Caucasus Abstract This study solves transport interconnection in the South Caucasus region with a focus on four modes of transport - air, rail, road and pipeline. The research covers regional cooperation and cross-border involvement of other states and international organizations. Literature and data research from statistical office of Armenia, Azerbaijan and Georgia sites, which I analyzed and confronted with the liberal theory of functionalism (neofunctionalism) and the opposite theory of realism (neorealism), was conducted. The result is an interdependence analysis evaluated at two ranks (regional and cross-border). It is followed by the applicability and summary of all political actors acting on the basis of liberal or realistic thinking. On the basis of the work there is possibility to build on research in the region of Central Asia. Keywords: South Caucasus; transport interconnection; Armenia; Azerbaijan; Georgia; geopolitics

The ever shrinking size of the MOS transistors brings the promise of scalable Network-on-Chip (NoC) architectures containing hundreds of processing elements with on-chip communication, all integrated into a single die. Such a computational fabric will provide high levels of performance in an energy efficient manner. To mitigate emerging wire-delay problem and to address the need for substantial interconnect bandwidth, packet switched routers are fast replacing shared buses and dedicated wires as the interconnect fabric of choice. With on-chip communication consuming a significant portion of the chip power and area budgets, there is a compelling need for compact, low power routers. While applications dictate the choice of the compute core, the advent of multimedia applications, such as 3D graphics and signal processing, places stronger demands for self-contained, low-latency floating-point processors with increased throughput. Therefore, this work focuses on two key building blocks critical to the success of NoC design: high performance, area and energy efficient router and floating-point processor architectures. This thesis first presents a six-port four-lane 57 GB/s non-blocking router core based on wormhole switching. The router features double-pumped crossbar channels and destinationaware channel drivers that dynamically configure based on the current packet destination. This enables 45% reduction in crossbar channel area, 23% overall router area, up to 3.8X reduction in peak channel power, and 7.2% improvement in average channel power, with no performance penalty over a published design. In a 150nm six-metal CMOS process, the 12.2mm2 router contains 1.9 million transistors and operates at 1GHz at 1.2V. We next present a new pipelined single-precision floating-point multiply accumulator core (FPMAC) featuring a single-cycle accumulate loop using base 32 and internal carry-save arithmetic, with delayed addition techniques. Combined algorithmic, logic and circuit techniques enable multiply-accumulates at speeds exceeding 3GHz, with single-cycle throughput. Unlike existing FPMAC architectures, the design eliminates scheduling restrictions between consecutive FPMAC instructions. The optimizations allow removal of the costly normalization step from the critical accumulate loop and conditionally powered down using dynamic sleep transistors on long accumulate operations, saving active and leakage power. In addition, an improved leading zero anticipator (LZA) and overflow detection logic applicable to carry-save format is presented. In a 90nm seven-metal dual-VT CMOS process, the 2mm2 custom design contains 230K transistors. The fully functional first silicon achieves 6.2 GFLOPS of performance while dissipating 1.2W at 3.1GHz, 1.3V supply. It is clear that realization of successful NoC designs require well balanced decisions at all levels: architecture, logic, circuit and physical design. Our results from key building blocks demonstrate the feasibility of pushing the performance limits of compute cores and communication routers, while keeping active and leakage power, and area under control. / Report code: LiU-TEK-LIC-2006:36.

Este trabalho apresenta um estudo sobre redes ópticas de interconexão aplicadas em arquiteturas paralelas, onde são propostos, simulados e analisados alguns modelos de redes. Essa é uma importante pesquisa, pois, as redes de interconexão influenciam diretamente o custo e desempenho das arquiteturas paralelas de computadores. O primeiro modelo de rede óptica proposto é chamado de SCF (Sistema Circular com Filas). Esse e um sistema sem colisões, onde há um canal exclusivo para controle de comunicação e cada nó possui um canal exclusivo para recepção de dados. Esse sistema tem um desempenho com alta taxa de vazão, alto nível de utilização e pequenas filas. Para a simulação da rede SCF foi desenvolvido um simulador dedicado, cuja adaptação para a simulação de outros modelos de redes, propostos nesse trabalho, foi facilmente realizada. Neste trabalho também foram propostos, simulados e analisados três modelos diferentes de chaves ópticas de distribuição para arquitetura paralela do tipo Dataflow. Os resultados dessas simulações mostram que componentes ópticos relativamente simples podem ser utilizados no desenvolvimento de sistemas de alto desempenho. / This work presents a study about optical interconnection network applied to parallel computer architectures, where is proposed, simulated and analyzed some models of optical interconnection networks. It is an important research because the interconnection networks influence directly the cost and performance of parallel computer architectures. The first optical interconnection network model proposed in this work is called SCF (Sistema Circular com Filas). It is a system without collisions, where there is a dedicated channel for communication control and each node has a fixed channel for data reception. The system has a performance with high throughput, high utilization leve1 and small queue size. For the SCF simulation was developed a dedicated simulator, whose adjust to simulate others optical interconnection network, proposed in this work, was easily performed. In this work also were proposed, simulated and analyzed three different models of optical distributing network for Dataflow computer architecture, whose results shows that single optical devises can ensure the development of high performance systems.

Live migration of Virtual Machines (VMs) has significantly improved the flexibility of modern Data Centers (DCs). Ideally, live migration ought to be seamless which in turn raises challenges on how to minimize service disruption and avoid performance degradation. To address these challenges, a comprehensive support from the underlying network is required. However, legacy DC networks fall short to help as they take a reactive approach to live migration procedure. Moreover, the complexity and inflexibility of legacy DC networks make it difficult to deploy, manage, and improve network technologies that DC providers may need to use for migration. In this thesis, we explore the application of Software Defined Networking (SDN) paradigm for making live VM migration more seamless. Exploiting the characteristics of SDN such as its centralized view on network states, we contribute to the body of knowledge by enhancing the quality of intra- and inter-DC live migration. Firstly, for intra-DC migration, we provide an SDN-based solution which minimizes the service disruption by employing OpenFlow-based resiliency mechanisms to prepare a DC network for migration proactively. Secondly, we improve the inter-DC live migration by accelerating the network convergence through announcing the migration in the control plane using MP-BGP protocol. Further, our proposed framework resolves the sub-optimal routing problem by conducting the gateway functionality at the SDN controller. Finally, with the ultimate goal of improving the inter-DC migration, we develop an SDN-based framework which automates the deployment, improves the management, enhances the performance, and increases the scalability of interconnections among DCs. / Live migration of Virtual Machines (VMs) has significantly improved the flexibility of modern Data Centers (DCs). Ideally, live migration ought to be seamless which requires a comprehensive support from the underlying network. However, legacy DC networks fall short to address the challenges of migration due to their inflexible and decentralized characteristics. In contrast, Software Defined Networking (SDN) is a new networking paradigm, which has the potential to improve the live migration thanks to its comprehensive view over the network, flexible structure, and its close integration with DC management infrastructures. This thesis investigates networking challenges of short and long-haul live VM migration in SDN-based DCs. We propose solutions to make the intra- and inter-DC live migration procedures more seamless. Furthermore, our proposed SDN-based framework for inter-DC migration improves the management, enhances the performance, and increases the scalability of interconnections among DCs. / HITS, 4707

There is a growing interest in the development of broadband services and networks for commercial use in both local area and wide area networks. The primary reasons for this is a pressing need to meet the demand for increased bandwidth for remote sites interconnection, and in high speed data transfer of bulk data such as images etc. There has also been a significant change in the characteristics of network traffic. It is increasingly taking the form of bursty traffic characterized by an unpredictable demand for bandwidth of several megabytes. A new generation of networking technologies have emerged to meet the demand of growing and uncertain bandwidth requirements. One such technology is called Asynchronous Transfer Mode (ATM) for use on broadband networks under the banner of broadband ISDN. ATM enables interconnection at high speeds in the range of Mbit/s or Gbit/s over wide areas, which effectively moves the bottleneck from networks to end systems. Furthermore, the user is able to access bandwidth on demand and the user is only charged for the bandwidth actually used. As more and more information (audio, image and data) is transferred over ATM networks, security issues are becoming increasingly critical. The rapidly growing use of the Internet to transfer confidential and sensitive information only enhances the importance of security services. One may even argue that the success of ATM will be determined not by its cost effectiveness but also to the level of trust that can be placed on its performance, security and availability. The objective of this dissertation is to address the issues involved in the design of security services for ATM networks. / Master of Science (Hons)

Degree awarded (2004): PhDEc, Economics, George Washington University / This research introduces a new theoretical framework for the analysis of access pricing (the prices that networks charge each other for the completion of calls) and the modeling of network interconnection competition. Prior work on two-way access by Armstrong (1998), Laffont, Rey and Tirole (1998), and Carter and Wright (1999), et al has been built on a two-network Hotelling (1929) differentiated competition model applied to network interconnection. The current research develops an alternative approach that is based on a cross-nested logit (CNL) discrete/continuous consumer choice model with a constant elasticity of substitution (CES) calling utility specification. A principal contribution of the new modeling framework is that in addition to being able to analyze interconnection competition among multiple networks, it is designed to incorporate the element of multiple network subscription where consumers may simultaneously subscribed to more than one type of access network. By introducing multiple-network subscription and usage substitution for users subscribed to multiple networks, the analysis allows more general assessments to be made of the impact of access pricing schemes on the degree of competition between interconnected networks. The model is also not restricted to assumptions of homogeneity in calling on the differentiated networks but can incorporate call differentiation according to network type. The model is applied to evaluate the effects of dual network subscription and asymmetric network competition and to assess multi-network competition in an environment served by two mobile networks and a fixed, wireline network. While confirming the results of prior single network subscription analysis, a central finding of the research based on the developed model is that while network competition is intensified when dual network subscription occurs, negotiated access charges between connected networks continue to serve as an instrument of collusion even in cases of non-linear (two-part) consumer tariffs. / Advisory Committee: John Kwoka, Christopher Snyder (Chair), Sumit Joshi

<p>The ever shrinking size of the MOS transistors brings the promise of scalable Network-on-Chip (NoC) architectures containing hundreds of processing elements with on-chip communication, all integrated into a single die. Such a computational fabric will provide high levels of performance in an energy efficient manner. To mitigate emerging wire-delay problem and to address the need for substantial interconnect bandwidth, packet switched routers are fast replacing shared buses and dedicated wires as the interconnect fabric of choice. With on-chip communication consuming a significant portion of the chip power and area budgets, there is a compelling need for compact, low power routers. While applications dictate the choice of the compute core, the advent of multimedia applications, such as 3D graphics and signal processing, places stronger demands for self-contained, low-latency floating-point processors with increased throughput. Therefore, this work focuses on two key building blocks critical to the success of NoC design: high performance, area and energy efficient router and floating-point processor architectures.</p><p>This thesis first presents a six-port four-lane 57 GB/s non-blocking router core based on wormhole switching. The router features double-pumped crossbar channels and destinationaware channel drivers that dynamically configure based on the current packet destination. This enables 45% reduction in crossbar channel area, 23% overall router area, up to 3.8X reduction in peak channel power, and 7.2% improvement in average channel power, with no performance penalty over a published design. In a 150nm six-metal CMOS process, the 12.2mm2 router contains 1.9 million transistors and operates at 1GHz at 1.2V. We next present a new pipelined single-precision floating-point multiply accumulator core (FPMAC) featuring a single-cycle accumulate loop using base 32 and internal carry-save arithmetic, with delayed addition techniques. Combined algorithmic, logic and circuit techniques enable multiply-accumulates at speeds exceeding 3GHz, with single-cycle throughput. Unlike existing FPMAC architectures, the design eliminates scheduling restrictions between consecutive FPMAC instructions. The optimizations allow removal of the costly normalization step from the critical accumulate loop and conditionally powered down using dynamic sleep transistors on long accumulate operations, saving active and leakage power. In addition, an improved leading zero anticipator (LZA) and overflow detection logic applicable to carry-save format is presented. In a 90nm seven-metal dual-VT CMOS process, the 2mm2 custom design contains 230K transistors. The fully functional first silicon achieves 6.2 GFLOPS of performance while dissipating 1.2W at 3.1GHz, 1.3V supply.</p><p>It is clear that realization of successful NoC designs require well balanced decisions at all levels: architecture, logic, circuit and physical design. Our results from key building blocks demonstrate the feasibility of pushing the performance limits of compute cores and communication routers, while keeping active and leakage power, and area under control.</p> / Report code: LiU-TEK-LIC-2006:36.

The subject of this thesis is a new chip to substrate interconnection technique using self-aligning elastic chip sockets. This work was focused on the technology steps which are necessary to fulfill in order to realize the suggested technique. Elastic chip sockets offer a solution for several assembly and packaging challenges, such a thermo-mechanical mismatch, effortless rework, environmental compatibility, high interconnection density, high frequency signal integrity, etc. Two of the most challenging technology aspects, metallization and etching of the silicone elastomer were studied, but also, air bubble free casting of the silicone elastomer was taken into consideration. Elastic chip sockets and single elastic micro-bump contacts of different shapes and sizes were manufactured and characterized. The contact resistance measurements revealed that the elastic micro-bump contacts manufactured by using the developed methods require less than one tenth of the contact force to achieve the same low contact resistance as compared to commercial elastic interconnection structures. The analysis and measurements of the high frequency properties of the elastic micro-bump structures have shown that they can operate up to several tens of GHz without a serious degradation of the signal quality. The same methods were applied to manufacture very high density contact area array (approximately 80000 connections/cm2), which until now was achieved only using so called chip-first techniques. The low contact resistance, the absence of environmentally harmful materials, no need of soldering, easy rework as well as capability of very high interconnecting density and very high frequency compatibility, indicates a high potential of this technique for assembly and packaging. Moreover, the presented technology of the silicone elastomer micromachining (metallization and RIE in particular) can be used for manufacturing of other microstructures, like chemical or biological micro reactors. / QC 20110114

This thesis presents the applications of a series interconnection scheme for small distributed generation (DG) systems in distribution networks. The concept uses one set of voltage source converter (VSC) to control the injected voltage magnitude and phase angle for power injection and voltage sag mitigation. Through an energy storage device and the VSC, DG outputs vary concurrently with the line loading and provide load leveling functions. Under voltage sag situations, it provides missing voltages to effectively deal with power quality problems. Due to its series connection characteristic, it is convenient in preventing islanding operation and good for fault current limiting. The concept is suitable for locations where the voltage phase shift is not a major concern. Due to the use of only one set of converter, it is economic for customer site distributed energy resource applications and its control strategy would depend on the types of load connected.

<p>The subject of this thesis is a new chip to substrate interconnection technique using self-aligning elastic chip sockets. This work was focused on the technology steps which are necessary to fulfill in order to realize the suggested technique. Elastic chip sockets offer a solution for several assembly and packaging challenges, such a thermo-mechanical mismatch, effortless rework, environmental compatibility, high interconnection density, high frequency signal integrity, etc.</p><p>Two of the most challenging technology aspects, metallization and etching of the silicone elastomer were studied, but also, air bubble free casting of the silicone elastomer was taken into consideration. Elastic chip sockets and single elastic micro-bump contacts of different shapes and sizes were manufactured and characterized.</p><p>The contact resistance measurements revealed that the elastic micro-bump contacts manufactured by using the developed methods require less than one tenth of the contact force to achieve the same low contact resistance as compared to commercial elastic interconnection structures.</p><p>The analysis and measurements of the high frequency properties of the elastic micro-bump structures have shown that they can operate up to several tens of GHz without a serious degradation of the signal quality.</p><p>The same methods were applied to manufacture very high density contact area array (approximately 80000 connections/cm2), which until now was achieved only using so called chip-first techniques.</p><p>The low contact resistance, the absence of environmentally harmful materials, no need of soldering, easy rework as well as capability of very high interconnecting density and very high frequency compatibility, indicates a high potential of this technique for assembly and packaging.</p><p>Moreover, the presented technology of the silicone elastomer micromachining (metallization and RIE in particular) can be used for manufacturing of other microstructures, like chemical or biological micro reactors.</p>