Computer engineering is advancing rapidly. For 55 years, the performance of integrated circuits has almost doubled every 18 months. Mostly, these advancements were enabled by technological progress. Even the end of frequency scaling could not bring the ever-increasing performance growth to a halt. However, technology burdens, like noticeable leakage currents, have piled up, which shifts the focus towards architectural improvements. Especially the multi-core paradigm has proven its virtue for chip designs over the last decade. While having been introduced in high-performance computing areas, modern technology nodes also enable low-cost, low-power embedded designs to benefi t from multiple cores and accelerators. Since the majority of cores depend on memory, which requires a considerable amount of chip area, this common resource needs to be shared effi ciently. High-performance cores use shared caches to increase memory utilization. However, many accelerators do not use caches as they need predictable and fast scratchpad memory (SM). But sharing SM entails confl icts, questioning its fast and predictable nature. Hence, the question arises on how to adapt architectures for sharing while retaining SM’s advantages. This thesis presents a novel, shared SM architecture that embraces the idea of a minimal logic path between core and memory, thereby increasing the maximum operating frequency. Because of its additional capabilities, like dynamic address translation and programmable priorities, it is also well suited for heterogeneous platforms that use dynamic scheduling and require predictable behavior. Demonstrating its advantages, we analyze the characteristics of the new architecture and compare it to state-of-the-art approaches. To further mitigate confl icts, we present the conception of access interval prediction (AIP). By predicting memory accesses with a granularity of a single clock cycle, AIP guides the allocation of resources. This method maximizes memory utilization while reducing confl ict delays. With the help of various methods inspired by branch prediction, we achieve over 90 % of accurate predictions and reduce stall cycles signifi cantly. Another key contribution of this thesis is the extension of analytic models to estimate the throughput of shared SM systems. Again, the focus lies on heterogeneous systems with different priorities and access patterns. The results show a promising error reduction, boosting the used models applicability for real design use cases.

時間序列是用來預測未來趨勢的一種重要技術，然而在實務上建構時間序列模型時，參數很難有效估計。原因可能來自於時間序列本身的模糊性質，而導致參數的不確定性使得預測結果產生極大誤差。如果將參數模糊化引進時間序列的模型中，往往過於複雜。本論文提出相對移動率為新的模糊時間序列建構方法，讓原本具有模糊性質的時間序列經由反模糊化(defuzzification)後，以點估計的方式估計起始中心點，經由適當的修正調整為較佳的中心點以及半徑，建立有效的區間時間序列。並將相對移動率引進門檻自廻規模型中，取代原有之門檻值設定，並建立區間時間序列。最後，我們使用台灣加權股價指數為例，以本論文所提出之方法進行區間預測及效率評估。 / The time series is an important technology that is used to predict future trends, however in the real world, parameter is difficult to estimate effectively when we construct a time series model due to the of the fuzzy property of the times series data. The estimated parameters in the time series will cause a big error due to the uncertainty of fuzzy data. It is too complex to introduce the fuzzy parameters into the time series model. In this thesis, we propose relative moving ratio as a new criteria in constructing procedure of an interval time series. We defuzzify a fuzzy data and use point estimation to obtain an initial center, then we adjust the center and radius making it more appropriately. The resulting center and radius is then become an interval time series that can be use to forecast an interval data. We also apply relative moving ratio in threshold autoregressive models by replacing the threshold in constructing interval time series. Finally, in empirical studies chapter, we use Taiwan weighted Stock Index as examples to evaluate the performance of the proposed two methods in building the interval time series.