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Deposition and characterization of thin films for applications in ULSI fabricationWang, Qi 28 August 2008 (has links)
Not available / text
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132 |
Thermal stress and stress relaxation in copper metallization for ULSI interconnectsGan, Dongwen 28 August 2008 (has links)
Not available / text
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133 |
New methodology for low power and less test time in VLSI testingLee, Il-Soo 28 August 2008 (has links)
Not available / text
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Nanometer VLSI placement and optimization for multi-objective design closureLuo, Tao, Ph. D. 29 August 2008 (has links)
Not available
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135 |
Memory-efficient, scalable ray tracingNavrátil, Paul Arthur 13 December 2010 (has links)
Ray tracing is an attractive rendering option because it can produce high quality images that faithfully represent physically-based phenomena. Its embarrassingly
parallel nature makes it a natural choice for rendering large-scale scene data, especially on machines that lack specialized graphics hardware. Unfortunately, the traditional recursive ray tracing algorithm is exceptionally memory inefficient for large scenes, especially when using a shading model that generates incoherent secondary rays. Queueing ray tracers have been shown to control scene state under these conditions, but they allow ray state to grow unchecked. Instead, we propose a ray tracing framework that controls both ray and scene state by dynamically adjusting the rendering algorithm to meet memory requirements. Our dynamic scheduling framework generalizes recursive and queueing tracers into a spectrum of ray schedules that can vary the active amount of ray and scene data in order to match the characteristics of the hardware’s memory system.
This dissertation describes our dynamic ray scheduling approach that operates on memory-bound work units, which consist of both rays and scene data. It builds these work units by tracing rays iteratively and queueing them in spatial regions along with nearby data. By dynamically scheduling these work units, our approach can reduce data loads and improve total runtime by 2x to 30x . In addition, we show that our algorithm scales across more than 1000 distributed processors, which is an order of magnitude larger than previously published results. Our approach enables the use of complex lighting models on large data, particularly
scientific data, which improves image quality and thereby improves the scientific insights possible. / text
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Ultra thin HfO₂ gate stack for sub-100nm ULSI CMOS technologyLee, Sungjoo 28 April 2011 (has links)
Not available / text
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Cell and interconnect timing analysis using waveformsCroix, John Francis, 1963- 10 May 2011 (has links)
Not available / text
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New algorithms for physical design of VLSI circuitsLai, Minghorng 10 May 2011 (has links)
Not available / text
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Minimum bounding boxes and volume decomposition of CAD modelsChan, Chi-keung, 陳志強 January 2003 (has links)
published_or_final_version / abstract / toc / Mechanical Engineering / Doctoral / Doctor of Philosophy
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A new optimization model for VLSI placement高雲龍, Ko, Wan-lung. January 1998 (has links)
published_or_final_version / abstract / toc / Electrical and Electronic Engineering / Master / Master of Philosophy
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