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by Li Wai Ting. / Thesis (M.Ph.)--Chinese University of Hong Kong, 1987. / Includes bibliographical references.

He, Xu. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2013. / Includes bibliographical references (leaves [127]-135). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstracts also in Chinese.

The ever-increasing design complexity of modern circuits challenges our ability to verify their correctness. Therefore, various errors are more likely to escape the pre-silicon verification process and to manifest themselves after design tape-out. To address this problem, effective post-silicon validation is essential for eliminating design bugs before integrated circuit (IC) products shipped to customers. In the debug process, it becomes increasingly popular to insert design-for-debug (DfD) structures into the original design to facilitate real-time debug without intervening the circuits’ normal operation. For this so-called trace-based post-silicon validation technique, the key question is how to design such DfD circuits to achieve sufficient observability and controllability during the debug process with limited hardware overhead. However, in today’s VLSI design flow, this is unfortunately conducted in a manual fashion based on designers’ own experience, which cannot guarantee debug quality. To tackle this problem, we propose a set of automatic tracing solutions as well as innovative DfD designs in this thesis. First, we develop a novel trace signal selection technique to maximize the visibility on debugging functional design errors. To strengthen the capability for tackling these errors, we sequentially introduce a multiplexed signal tracing strategy with a trace signal grouping algorithm for maximizing the probability of catching the propagated evidences from functional design errors. Then, to effectively localize speedpathrelated electrical errors, we propose an innovative trace signal selection solution as well as a trace qualification technique. On the other hand, we introduce several low-cost interconnection fabrics to effectively transfer trace data in post-silicon validation. We first propose to reuse the existing test channel for real-time trace data transfer, so that the routing cost of debug hardware is dramatically reduced. The method is further improved to avoid data corruption in multi-core debug. We then develop a novel interconnection fabric design and optimization technique, by combining multiplexor network and non-blocking network, to achieve high debug flexibility with minimized hardware cost. Moreover, we introduce a hybrid trace interconnection fabric that is able to tolerate unknown values in “golden vectors“, at the cost of little extra DfD overhead. With the fabric, we develop a systematic signal tracing procedure to automatically localize erroneous signals with just a few debug runs. Our empirical evaluation shows that the solutions presented in this thesis can greatly improve the validation quality of VLSI circuits, and ultimately enable the design and fabrication of reliable electronic devices. / Liu, Xiao. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2012. / Includes bibliographical references (leaves 143-152). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract --- p.i / Acknowledgement --- p.iv / Preface --- p.vii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- VLSI Design Trends and Validation Challenges --- p.1 / Chapter 1.2 --- Key Contributions and Thesis Outline --- p.4 / Chapter 2 --- State of the Art on Post-Silicon Validation --- p.8 / Chapter 2.1 --- Trace Signal Selection --- p.12 / Chapter 2.2 --- Interconnection Fabric Design for Trace Data Transfer --- p.14 / Chapter 2.3 --- Trace Data Compression --- p.15 / Chapter 2.4 --- Trace-Based Debug Control --- p.16 / Chapter 3 --- Signal Selection for Visibility Enhancement --- p.18 / Chapter 3.1 --- Preliminaries and Summary of Contributions --- p.19 / Chapter 3.2 --- Restorability Formulation --- p.23 / Chapter 3.2.1 --- Terminologies --- p.23 / Chapter 3.2.2 --- Gate-Level Restorabilities --- p.24 / Chapter 3.3 --- Trace Signal Selection --- p.28 / Chapter 3.3.1 --- Circuit Level Visibility Calculation --- p.28 / Chapter 3.3.2 --- Trace Signal Selection Methodology --- p.30 / Chapter 3.3.3 --- Trace Signal Selection Enhancements --- p.31 / Chapter 3.4 --- Experimental Results --- p.34 / Chapter 3.4.1 --- Experiment Setup --- p.34 / Chapter 3.4.2 --- Experimental Results --- p.35 / Chapter 3.5 --- Conclusion --- p.40 / Chapter 4 --- Multiplexed Tracing for Design Error --- p.47 / Chapter 4.1 --- Preliminaries and Summary of Contributions --- p.49 / Chapter 4.2 --- Design Error Visibility Metric --- p.53 / Chapter 4.3 --- Proposed Methodology --- p.56 / Chapter 4.3.1 --- Supporting DfD Hardware for Multiplexed Signal Tracing --- p.58 / Chapter 4.3.2 --- Signal Grouping Algorithm --- p.58 / Chapter 4.4 --- Experimental Results --- p.62 / Chapter 4.4.1 --- Experiment Setup --- p.62 / Chapter 4.4.2 --- Experimental Results --- p.63 / Chapter 4.5 --- Conclusion --- p.66 / Chapter 5 --- Tracing for Electrical Error --- p.68 / Chapter 5.1 --- Preliminaries and Summary of Contributions --- p.69 / Chapter 5.2 --- Observing Speedpath-Related Electrical Errors --- p.71 / Chapter 5.2.1 --- Speedpath-Related Electrical Error Model --- p.71 / Chapter 5.2.2 --- Speedpath-Related Electrical Error Detection Quality --- p.73 / Chapter 5.3 --- Trace Signal Selection --- p.75 / Chapter 5.3.1 --- Relation Cube Extraction --- p.76 / Chapter 5.3.2 --- Signal Selection for Non-Zero-Probability Error Detection --- p.77 / Chapter 5.3.3 --- Trace Signal Selection for Error Detection Quality Enhancement --- p.78 / Chapter 5.4 --- Trace Data Qualification --- p.80 / Chapter 5.5 --- Experimental Results --- p.83 / Chapter 5.6 --- Conclusion --- p.87 / Chapter 6 --- Reusing Test Access Mechanisms --- p.88 / Chapter 6.1 --- Preliminaries and Summary of Contributions --- p.89 / Chapter 6.1.1 --- SoC Test Architectures --- p.89 / Chapter 6.1.2 --- SoC Post-Silicon Validation Architectures --- p.90 / Chapter 6.1.3 --- Summary of Contributions --- p.92 / Chapter 6.2 --- Overview of the Proposed Debug Data Transfer Framework --- p.93 / Chapter 6.3 --- Proposed DfD Structures --- p.94 / Chapter 6.3.1 --- Modified Wrapper Design --- p.95 / Chapter 6.3.2 --- Trace Buffer Interface Design --- p.97 / Chapter 6.4 --- Sharing TAM for Multi-Core Debug Data Transfer --- p.98 / Chapter 6.4.1 --- Core Masking for TestRail Architecture --- p.98 / Chapter 6.4.2 --- Channel Split --- p.99 / Chapter 6.5 --- Experimental Results --- p.101 / Chapter 6.6 --- Conclusion --- p.104 / Chapter 7 --- Interconnection Fabric for Flexible Tracing --- p.105 / Chapter 7.1 --- Preliminaries and Summary of Contributions --- p.106 / Chapter 7.2 --- Proposed Interconnection Fabric Design --- p.111 / Chapter 7.2.1 --- Multiplexer Network for Mutually-Exclusive Signals --- p.111 / Chapter 7.2.2 --- Non-Blocking Concentration Network for Concurrently-Accessible Signals --- p.114 / Chapter 7.3 --- Experimental Results --- p.117 / Chapter 7.4 --- Conclusion --- p.121 / Chapter 8 --- Interconnection Fabric for Systematic Tracing --- p.123 / Chapter 8.1 --- Preliminaries and Summary of Contributions --- p.124 / Chapter 8.2 --- Proposed Trace Interconnection Fabric --- p.128 / Chapter 8.3 --- Proposed Error Evidence Localization Methodology --- p.130 / Chapter 8.4 --- Experimental Results --- p.133 / Chapter 8.4.1 --- Experimental Setup --- p.133 / Chapter 8.4.2 --- Results and Discussion --- p.134 / Chapter 8.5 --- Conclusion --- p.139 / Chapter 9 --- Conclusion --- p.140 / Bibliography --- p.152

VLSI testing poses a number of problems which includes the selection of test techniques, the determination of acceptable fault coverage levels, and test vector generation. Available device test techniques are examined and compared. Design rules should be employed to assure the design is testable. Logic simulation systems and available test utilities are compared. The various methods of test vector generation are also examined. The selection criteria for test techniques are identified. A table of proposed design rules is included. Testability measurement utilities can be used to statistically predict the test generation effort. Field reject rates and fault coverage are statistically related. Acceptable field reject rates can be achieved with less than full test vector fault coverage. The methods and techniques which are examined form the basis of the recommended integrated test plan. The methods of automatic test vector generation are relatively primitive but are improving.

No description available.

Ph.D. / Electrical Engineering / Nanometer-scale devices have attracted great attention as the ultimate evolution of silicon integrated circuit technology. However, fabrication of nanometer-scale silicon based devices has met great difficulty because it places severe constraints on process technology. This is especially true for SiGe/Si heterostructures because they are particularly sensitive to strain relaxation and/or process induced defects. Recently developed Pulsed Laser Induced Epitaxy (PLIE) offers a promising approach for the fabrication of nanometer- scale SiGe/Si devices. It possesses the advantage of ultra-short time, low thermal budget and full compatibility with current silicon technology. The selective nature of the process allows epitaxial growth of high quality, localized SiGe layers in silicon. In this thesis, a process to fabricate SiGe nanowires in silicon using PLIE is described. In particular, Ge nanowires with a cross-section of ~6 x 60 nm² are first formed using a lift-off process on the silicon substrate with e-beam lithography, followed by a thin low-temperature oxide deposition. Defect-free SiGe nanowires with a cross-section of ~25 x 95 nm² are then produced by impinging the laser beam on the sample. We thus demonstrate PLIE is a suitable fabrication technique for SiGe/Si nanostructures. Fabrication of Ge nanowires is also studied using Focused Ion Beam (FIB) micromachining techniques. Based on the SiGe nanowire process, we propose two advanced device structures, a quantum wire MOSFET and a lateral SiGe Heterojunction Bipolar Transistor (HBT). MEDICI simulation of the lateral SiGe HBT demonstrates high performance of the device. In order to characterize the SiGe nanowires using cross-sectional transmission electron microscopy, an advanced versatile focused ion beam assisted sample preparation technique using a multi-layer stack scheme for localized surface structures is developed and described in this thesis.