by Man-chung Suen. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1994. / Includes bibliographical references (leaves [123]-[126]). / Acknowledgement --- p.ii / Abstract --- p.iii / List of Tables --- p.vii / List of Figures --- p.xii / Chapter 1 --- Introduction --- p.1 / Chapter 2 --- Approach to Find the Equivalent Models --- p.5 / Chapter 2.1 --- Scattering Parameters of the Microstrip Structure --- p.5 / Chapter 2.2 --- Optimization Process --- p.7 / Chapter 2.3 --- Summary --- p.8 / Chapter 3 --- Microstrip Discontinuities Being Modelled --- p.9 / Chapter 3.1 --- Right-Angled Bend --- p.9 / Chapter 3.2 --- T-Junction --- p.10 / Chapter 3.3 --- Tapered Line --- p.10 / Chapter 4 --- Deficiency of Lumped Equivalent Circuits --- p.13 / Chapter 4.1 --- Scattering Parameter of the T-Network --- p.13 / Chapter 4.2 --- Optimization Result for the T-Network --- p.14 / Chapter 4.3 --- Summary --- p.15 / Chapter 5 --- Proposed Wideband Equivalent Circuits --- p.17 / Chapter 5.1 --- Model of a Uniform Non-Homogeneous Microstrip Line --- p.17 / Chapter 5.2 --- Right-Angled Bend --- p.22 / Chapter 5.2.1 --- Circuit 1L --- p.24 / Chapter 5.2.2 --- Circuit 2L --- p.25 / Chapter 5.2.3 --- Circuit 3L --- p.26 / Chapter 5.2.4 --- Circuit 4L --- p.27 / Chapter 5.3 --- T-Junction --- p.28 / Chapter 5.3.1 --- Circuit IT --- p.28 / Chapter 5.3.2 --- Circuit 2T --- p.31 / Chapter 5.3.3 --- Circuit 3T --- p.31 / Chapter 5.3.4 --- Circuit 4T --- p.34 / Chapter 5.4 --- Tapered Line --- p.36 / Chapter 5.4.1 --- Circuit It -n =3 --- p.37 / Chapter 5.5 --- Summary --- p.38 / Chapter 6 --- Performance of the Equivalent Circuits --- p.39 / Chapter 6.1 --- Right-Angled Bend --- p.40 / Chapter 6.1.1 --- Without Conductor Loss --- p.40 / Chapter 6.1.2 --- With Conductor Loss --- p.48 / Chapter 6.2 --- T-Junction --- p.49 / Chapter 6.2.1 --- Without Conductor Loss --- p.53 / Chapter 6.2.2 --- With Conductor Loss --- p.63 / Chapter 6.3 --- Tapered Line --- p.69 / Chapter 6.3.1 --- Without Conductor Loss --- p.69 / Chapter 6.3.2 --- With Conductor Loss --- p.72 / Chapter 6.4 --- Summary --- p.73 / Chapter 7 --- Modelling Performance Using TEM Approximation --- p.77 / Chapter 7.1 --- Right-Angled Bend --- p.77 / Chapter 7.1.1 --- Without Conductor Loss --- p.78 / Chapter 7.1.2 --- With Conductor Loss --- p.87 / Chapter 7.2 --- T-Junction --- p.92 / Chapter 7.2.1 --- Without Conductor Loss --- p.92 / Chapter 7.2.2 --- With Conductor Loss --- p.104 / Chapter 7.3 --- Tapered Line --- p.115 / Chapter 7.3.1 --- Without Conductor Loss --- p.116 / Chapter 7.3.2 --- With Conductor Loss --- p.117 / Chapter 7.4 --- Summary --- p.117 / Chapter 8 --- Conclusion --- p.120 / Bibliography --- p.123

by Tsz Shing Cheung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1990. / Includes bibliographical references. / Chapter Section 1 --- Introduction --- p.2 / Chapter 1.1 --- The Affinity Clustering Phase --- p.2 / Chapter 1.2 --- The Alteration Phase --- p.3 / Chapter 1.3 --- Floorplan of Macrocell Array --- p.3 / Chapter 1.4 --- Chip Model --- p.4 / Chapter 1.4.1 --- Location Representation --- p.4 / Chapter 1.4.2 --- Interconnection Length Estimation --- p.6 / Chapter 1.5 --- Cost Function Evaluation --- p.6 / Chapter 1.5.1 --- Net-length Calculation --- p.6 / Chapter 1.5.2 --- Net-length Estimated by Half of the Perimeter of Bounding Box --- p.7 / Chapter 1.6 --- Thesis Layout --- p.8 / Chapter Section 2 --- Reviews of Partitioning and Placement Methods --- p.9 / Chapter 2.1 --- Partitioning Methods --- p.9 / Chapter 2.1.1 --- Direct Method --- p.10 / Chapter 2.1.2 --- Group Migration Method --- p.10 / Chapter 2.1.3 --- Metric Allocation Methods --- p.10 / Chapter 2.1.4 --- Simulated Annealing --- p.11 / Chapter 2.2 --- Placement Methods --- p.12 / Chapter 2.2.1 --- Min-cut Methods --- p.13 / Chapter 2.2.2 --- Affinity Clustering Methods --- p.13 / Chapter 2.2.3 --- Other Placement Methods --- p.16 / Chapter Section 3 --- Algorithm --- p.17 / Chapter 3.1 --- The Affinity Clustering Phase --- p.18 / Chapter 3.1.1 --- Construction of Connection Lists --- p.18 / Chapter 3.1.2 --- Primary Grouping --- p.21 / Chapter 3.1.3 --- Element Appendage to Existing Groups --- p.23 / Chapter 3.1.4 --- Loose Appendage of Ungrouped Elements --- p.25 / Chapter 3.1.5 --- Single Element Groups Formation --- p.26 / Chapter 3.2 --- The Alteration Phase --- p.27 / Chapter 3.2.1 --- Element Assignment to a Group --- p.29 / Chapter 3.2.2 --- Empty Space Searching --- p.30 / Chapter 3.2.3 --- Determination of Direction of Element Allocation --- p.31 / Chapter 3.2.3.1 --- Cross-cut Direction of Allocation --- p.32 / Chapter 3.2.3.2 --- Dynamic Determination of Path Based on Size Functions --- p.34 / Chapter 3.2.3.2.1 --- Segmentation of Cross-cut --- p.35 / Chapter 3.2.3.2.2 --- Partial Optimization of Segments --- p.36 / Chapter 3.2.3.2.3 --- Dynamic Linking of Segments --- p.38 / Chapter 3.2.4 --- Element Allocation --- p.39 / Chapter Section 4 --- Implementation --- p.41 / Chapter 4.1 --- The System Row --- p.41 / Chapter 4.1.1 --- The Affinity Clustering Phase --- p.43 / Chapter 4.1.2 --- The Alteration Phase --- p.44 / Chapter 4.2 --- Data Structures --- p.47 / Chapter 4.2.1 --- Insertion of Elements to a Linked List --- p.54 / Chapter 4.2.2 --- Dynamic Linking of Segments --- p.56 / Chapter 4.2.3 --- Advantages of the Dynamic Data Structure --- p.59 / Chapter 4.3 --- Data Manipulation and File Management --- p.60 / Chapter 4.3.1 --- The Connection Lists and the Group List --- p.60 / Chapter 4.3.2 --- Description on Programs and Data Files --- p.62 / Chapter 4.3.2.1 --- The Affinity Clustering Phase --- p.63 / Chapter 4.3.2.2 --- The Alteration Phase --- p.64 / Chapter Section 5 --- Results --- p.70 / Chapter 5.1 --- Results on Affinity Clustering Phase --- p.84 / Chapter 5.2 --- Details of Affinity Clustering Procedure on Ckt. 2 and Ckt. 5 --- p.92 / Chapter 5.3 --- Results on Alteration Phase --- p.97 / Chapter 5.4 --- Details of Alteration Procedure on Ckt. 2 and Ckt. 5 --- p.101 / Chapter Section 6 --- Discussion --- p.107 / Chapter 6.1 --- Computation Time of the Algorithm --- p.107 / Chapter 6.2 --- Alternative Methods on the Determination of Propagation Path --- p.110 / Chapter 6.2.1 --- Method 1 --- p.110 / Chapter 6.2.2 --- Method 2 --- p.111 / Chapter 6.2.3 --- Method 3 --- p.114 / Chapter 6.2.4 --- Comparison on Execution Time of the Four Methods --- p.117 / Chapter 6.3 --- Wiring Optimization --- p.118 / Chapter 6.3.1 --- Data Structure --- p.119 / Chapter 6.3.2 --- Overlapping and Separate Bounding Boxes --- p.120 / Chapter 6.4 --- Generalization of the Data Structure --- p.122 / Chapter 6.4.1 --- Cell Types --- p.123 / Chapter 6.4.2 --- Adhesive Attributes --- p.124 / Chapter 6.4.3 --- Blocks Representation --- p.124 / Chapter 6.4.4 --- Critical Path Adjustment --- p.125 / Chapter 6.4.5 --- Total Interconnection Length Estimation --- p.129 / Chapter 6.5 --- A New Placement Algorithm --- p.130 / Chapter 6.6 --- An Alternative Method on Element Allocation --- p.132 / Chapter Section 7 --- Conclusion --- p.136 / Chapter Section 8 --- References --- p.138 / Chapter Section 9 --- Appendix I --- p.142 / Chapter 9.1 --- Definition of the Problem --- p.142 / Chapter 9.2 --- The Simulated Annealing Algorithm --- p.142 / Chapter 9.3 --- Example Circuit --- p.143 / Chapter 9.4 --- Performance Indices and Energy Value --- p.144 / Chapter 9.4.1 --- Total Interconnection Length --- p.144 / Chapter 9.4.2 --- Delay on Critical Paths --- p.144 / Chapter 9.4.3 --- Skew in Input-to-Output Delays --- p.146 / Chapter 9.4.4 --- Energy Value --- p.146 / Chapter 9.5 --- The Simulation Program --- p.146 / Chapter 9.5.1 --- "The ""function"" Subroutines" --- p.147 / Chapter 9.5.1.1 --- alise --- p.147 / Chapter 9.5.1.2 --- max delay --- p.147 / Chapter 9.5.1.3 --- replace --- p.147 / Chapter 9.5.1.4 --- total length --- p.147 / Chapter 9.5.2 --- "The ""procedure"" Subroutines" --- p.148 / Chapter 9.5.2.1 --- init_weight --- p.148 / Chapter 9.5.2.2 --- inverse --- p.148 / Chapter 9.5.2.3 --- initial --- p.148 / Chapter 9.5.2.4 --- shuffle --- p.148 / Chapter 9.5.3 --- The Main Program --- p.148 / Chapter 9.6 --- Results and Discussion --- p.149 / Chapter 9.7 --- Summary --- p.156 / Chapter 9.8 --- References --- p.156 / Chapter Section 10 --- Appendix II --- p.157

by Chan Lap-kong. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1994. / Includes bibliographical references (leaves 77-80). / ABSTRACT / ACKNOWLEDGEMENTS / LIST OF FIGURES / Chapter 1. --- INTRODUCTION --- p.1 / Chapter 1.1 --- Background --- p.1 / Chapter 1.2 --- Problems in Testing VLSI Circuits --- p.3 / Chapter 1.2.1 --- Test-cost-per-gate --- p.3 / Chapter 1.2.2 --- Tester Complexity --- p.3 / Chapter 1.3 --- Tester Based on Terminals Characteristics -Automatic Testing Equipment(ATE) --- p.4 / Chapter 1.4 --- Tester Based on Terminal and Internal Characteristics --- p.6 / Chapter 1.4.1 --- Mechanical Probing Method --- p.6 / Chapter 1.4.2 --- E-beam Probing Method --- p.7 / Chapter 1.5 --- Movitation for this Research --- p.7 / Chapter 1.6 --- Outline of the Remaining Chapters --- p.9 / Chapter 2. --- E-BEAM TESTER --- p.10 / Chapter 2.1 --- State-of-art of E-Beam Tester --- p.10 / Chapter 2.2 --- An Electron-optical Column of a SEM --- p.12 / Chapter 2.3 --- Beam Rastering Methods --- p.13 / Chapter 2.4 --- Voltage Contrast Phenomenon --- p.14 / Chapter 2.5 --- Configuration of an E-Beam Test System --- p.18 / Chapter 2.6 --- Advantages of an E-beam Tester --- p.20 / Chapter 3. --- BASIC PRINCIPLES --- p.21 / Chapter 3.1 --- Single-Stuck-At Fault Model --- p.21 / Chapter 3.2 --- Observability and Controllability --- p.24 / Chapter 3.3 --- Netlist Format --- p.25 / Chapter 3.4 --- Level --- p.27 / Chapter 3.5 --- Reconvergent Fanout --- p.28 / Chapter 4. --- CONVENTIONAL TEST GENERATION --- p.29 / Chapter 4.1 --- Conventional Automatic Test Generation for ATEs --- p.29 / Chapter 4.3 --- Conventional E-Beam Test Generation --- p.31 / Chapter 5. --- TEST AND PROBE POINT GENERATION --- p.32 / Chapter 5.1 --- Wafer Stage E-beam Testing --- p.32 / Chapter 5.2 --- Critical Paths Generation --- p.33 / Chapter 5.3 --- Assumptions of the Test and Probe Point Generation Algorithm --- p.35 / Chapter 5.4 --- Rules of the Test and Probe Point Generation Algorithm --- p.36 / Chapter 5.5 --- Probe Points Selection and Reduction --- p.38 / Chapter 5.6 --- Test and Probe Point Generation Algorithm --- p.40 / Chapter 5.7 --- Propagation and Justification at Fanout Site --- p.42 / Chapter 6. --- EXAMPLES --- p.45 / Chapter 6.1 --- Example of Test and Probe Point Generation for Circuit sc2 --- p.45 / Chapter 6.2 --- Example of Test and Probe Point Generation for Circuit sfc4 --- p.53 / Chapter 7. --- CONCLUSIONS --- p.61 / Chapter 7.1 --- Summary of Results --- p.61 / Chapter 7.2 --- Further Research --- p.63 / APPENDIX / Appendix A: Algorithm to Find Reconvergent Fanouts / Appendix B: Results of Test Generation for Circuit sc1 / Appendix C: Results of Test Generation for Circuit sc3 / REFERENCES --- p.77

by Wai-Hung Leung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1995. / Includes bibliographical references (leaves 73-75). / Chapter 1 --- Introduction --- p.1 / Chapter 2 --- Wavelet Theory --- p.5 / Chapter 2-1 --- Basic Wavelet Theories --- p.5 / Chapter 2-2 --- Example of Haar Wavelet Base --- p.6 / Chapter 2-3 --- Wavelet Decomposition and Reconstruction with Multiresolution Analysis --- p.12 / Chapter 2-4 --- Conditions for the Effective Filter Bank and the Constructions of the Filter Coefficients --- p.17 / Chapter 2-5 --- Comparison between Wavelet Analysis and Fourier Analysis --- p.20 / Chapter 3 --- Waveform Relaxation Analysis of Distributed Network --- p.25 / Chapter 3-1 --- Introduction --- p.25 / Chapter 3-2 --- Method of Characteristics for the Simulation of Transmission Lines --- p.27 / Chapter 3-3 --- Waveform Relaxation Algorithm --- p.30 / Chapter 3-4 --- Pade Synthesis of Lossy Characteristic Impedance --- p.33 / Chapter 4 --- Application of FFT on the Transient Simulation of Distributed Network --- p.39 / Chapter 4-1 --- Simulation of Wave Propagation in Lossy Transmission Line with FFT --- p.39 / Chapter 4-2 --- Some Special Properties of the Wave Propagation Function of Lossy Transmission Lines --- p.44 / Chapter 5 --- Wavelet-based Convolution --- p.49 / Chapter 5-1 --- Introduction --- p.49 / Chapter 5-2 --- Application of Wavelet-based Convolution on the Simulation of Wave Propagation Function and Waveform Transformation --- p.58 / Chapter 6 --- Experimental Results of using Wavelet- based Convolution on the Transient Simulation of Lossy Transmission Lines --- p.64 / Chapter 7 --- Conclusions and Prospective Studies --- p.71 / Chapter 8 --- References --- p.73 / Appendix Program Lists --- p.76

Ku Man-Ho. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1995. / Includes bibliographical references (leaves 86-87). / Chapter 1. --- Introduction / Chapter 1.1. --- Introduction --- p.1 / Chapter 1.2. --- Power Noise --- p.2 / Chapter 1.3. --- High Speed Output Driver Design --- p.3 / Chapter 2. --- Power Bus Noise Analysis / Chapter 2.1. --- Introduction --- p.7 / Chapter 2.2. --- The Power bus model of a packed VLSI chip --- p.7 / Chapter 2.3. --- The effects of bonding wire on Power bus --- p.11 / Chapter 2.4. --- Noise analysis of multi-driver switching --- p.15 / Chapter 3. --- Effects of Power bus noise / Chapter 3.1. --- Introdcution --- p.22 / Chapter 3.2. --- Digital noise definition --- p.22 / Chapter 3.3. --- Static CMOS Inverter --- p.23 / Chapter 3.4. --- Dynamic gate --- p.32 / Chapter 4. --- Output Driver Design / Chapter 4.1. --- Introduction --- p.37 / Chapter 4.2. --- Optimum Discharge Current Waveform --- p.37 / Chapter 4.3. --- Simple Inverter Output driver --- p.40 / Chapter 4.4. --- Weighted and Distributed Driver --- p.42 / Chapter 4.5. --- Short circuit current prevention circuit --- p.50 / Chapter 5.6. --- Adaptive output driver --- p.52 / Chapter 5. --- Test chip Implementation / Chapter 5.1. --- Introduction --- p.57 / Chapter 5.2. --- Output Driver Circuit Design --- p.57 / Chapter 5.3. --- Simulation Results --- p.62 / Chapter 5.4. --- Test chip circuit --- p.65 / Chapter 5.5. --- Physical design --- p.67 / Chapter 6. --- Test Chip evaluation / Chapter 6.1. --- Introduction --- p.75 / Chapter 6.2. --- Rise time and overshoot Test --- p.76 / Chapter 6.3. --- Switching noise --- p.79 / Chapter 6.4. --- Driving Test --- p.82 / Chapter 7. --- Conslusions --- p.84 / Chapter 8. --- References --- p.86 / Chapter 9. --- Appendix A --- p.88 / Chapter 10. --- Appendix B --- p.91 / Chapter 11. --- Appendix C --- p.100 / Chapter 12. --- Appendix D --- p.101 / Chapter 13. --- Appendix E --- p.102

Yuen Wing-seung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2001. / Includes bibliographical references (leaves [116]-[122]). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgments --- p.iii / List of Figures --- p.viii / List of Tables --- p.xii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivations and Aims --- p.1 / Chapter 1.2 --- Contributions --- p.3 / Chapter 1.3 --- Dissertation Overview --- p.4 / Chapter 2 --- Physical Design and Floorplanning in VLSI Circuits --- p.6 / Chapter 2.1 --- VLSI Design Flow --- p.6 / Chapter 2.2 --- Floorplan Design --- p.8 / Chapter 2.2.1 --- Problem Formulation --- p.9 / Chapter 2.2.2 --- Types of Floorplan --- p.10 / Chapter 3 --- Floorplanning Representations --- p.12 / Chapter 3.1 --- Polish Expression(PE) [WL86] --- p.12 / Chapter 3.2 --- Bounded-Sliceline-Grid(BSG) [NFMK96] --- p.14 / Chapter 3.3 --- Sequence Pair(SP) [MFNK95] --- p.17 / Chapter 3.4 --- O-tree(OT) [GCY99] --- p.19 / Chapter 3.5 --- B*-tree(BT) [CCWW00] --- p.21 / Chapter 3.6 --- Corner Block List(CBL) [HHC+00] --- p.22 / Chapter 4 --- Optimization Technique in Floorplan Design --- p.27 / Chapter 4.1 --- General Optimization Methods --- p.27 / Chapter 4.1.1 --- Simulated Annealing --- p.27 / Chapter 4.1.2 --- Genetic Algorithm --- p.29 / Chapter 4.1.3 --- Integer Programming Method --- p.31 / Chapter 4.2 --- Shape Optimization --- p.33 / Chapter 4.2.1 --- Shape Curve --- p.33 / Chapter 4.2.2 --- Lagrangian Relaxation --- p.34 / Chapter 5 --- Literature Review on Interconnect Driven Floorplanning --- p.37 / Chapter 5.1 --- Placement Constraint in Floorplan Design --- p.37 / Chapter 5.1.1 --- Boundary Constraints --- p.37 / Chapter 5.1.2 --- Pre-placed Constraints --- p.39 / Chapter 5.1.3 --- Range Constraints --- p.41 / Chapter 5.1.4 --- Symmetry Constraints --- p.42 / Chapter 5.2 --- Timing Analysis Method --- p.43 / Chapter 5.3 --- Buffer Block Planning and Congestion Control --- p.45 / Chapter 5.3.1 --- Buffer Block Planning --- p.45 / Chapter 5.3.2 --- Congestion Control --- p.50 / Chapter 6 --- Clustering Constraint in Floorplan Design --- p.53 / Chapter 6.1 --- Problem Definition --- p.53 / Chapter 6.2 --- Overview --- p.54 / Chapter 6.3 --- Locating Neighboring Modules --- p.56 / Chapter 6.4 --- Constraint Satisfaction --- p.62 / Chapter 6.5 --- Multi-clustering Extension --- p.64 / Chapter 6.6 --- Cost Function --- p.64 / Chapter 6.7 --- Experimental Results --- p.65 / Chapter 7 --- Interconnect Driven Multilevel Floorplanning Approach --- p.69 / Chapter 7.1 --- Multilevel Partitioning --- p.69 / Chapter 7.1.1 --- Coarsening Phase --- p.70 / Chapter 7.1.2 --- Refinement Phase --- p.70 / Chapter 7.2 --- Overview of Multilevel Floorplanner --- p.72 / Chapter 7.3 --- Clustering Phase --- p.73 / Chapter 7.3.1 --- Clustering Methods --- p.73 / Chapter 7.3.2 --- Area Ratio Constraints --- p.75 / Chapter 7.3.3 --- Clustering Velocity --- p.76 / Chapter 7.4 --- Refinement Phase --- p.77 / Chapter 7.4.1 --- Temperature Control --- p.79 / Chapter 7.4.2 --- Cost Function --- p.80 / Chapter 7.4.3 --- Handling Shape Flexibility --- p.80 / Chapter 7.5 --- Experimental Results --- p.81 / Chapter 7.5.1 --- Data Set Generation --- p.82 / Chapter 7.5.2 --- Temperature Control --- p.82 / Chapter 7.5.3 --- Packing Results --- p.83 / Chapter 8 --- Study of Non-slicing Floorplan Representations --- p.89 / Chapter 8.1 --- Analysis of Different Floorplan Representations --- p.89 / Chapter 8.1.1 --- Complexity --- p.90 / Chapter 8.1.2 --- Types of Floorplans --- p.92 / Chapter 8.2 --- T-junction Orientation Property --- p.97 / Chapter 8.3 --- Twin Binary Tree Representation for Mosaic Floorplan --- p.103 / Chapter 8.3.1 --- Previous work --- p.103 / Chapter 8.3.2 --- Twin Binary Tree Construction --- p.105 / Chapter 8.3.3 --- Floorplan Construction --- p.109 / Chapter 9 --- Conclusion --- p.114 / Chapter 9.1 --- Summary --- p.114 / Bibliography --- p.116 / Chapter A --- Clustering Constraint Data Set --- p.123 / Chapter A.1 --- ami33 --- p.123 / Chapter A.1.1 --- One cluster --- p.123 / Chapter A.1.2 --- Multi-cluster --- p.123 / Chapter A.2 --- ami49 --- p.124 / Chapter A.2.1 --- One cluster --- p.124 / Chapter A.2.2 --- Multi-cluster --- p.124 / Chapter A.3 --- playout --- p.124 / Chapter A.3.1 --- One cluster --- p.124 / Chapter A.3.2 --- Multi-cluster --- p.125 / Chapter B --- Multilevel Data Set --- p.126 / Chapter B.l --- data_100 --- p.126 / Chapter B.2 --- data_200 --- p.127 / Chapter B.3 --- data_300 --- p.129 / Chapter B.4 --- data_400 --- p.131 / Chapter B.5 --- data_500 --- p.133

Thesis (B.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1981. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING. / by James Joseph Koschella. / B.S.

by Ronald Siu-kwong, Ip. / "June 1999." / Thesis (Ph.D.)--Chinese University of Hong Kong, 1999. / Includes bibliographical references (p. 89-94). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Mode of access: World Wide Web. / Abstracts in English and Chinese.

Two dimensional (2D) materials have been explosively researched since the discovery of graphene but the applications of 2D materials have been extremely constrained because of a variety of shortcomings in the materials such as zero bandgap in graphene or defective growth techniques for wide-bandgap materials. Nonetheless, such novel materials are very promising in the doomed situation which Moore’s law keeps slowing down. Graphene and αMoO3 have been particularly of interest because graphene has developed large-scale growth methods and αMoO3 has wide bandgap. In case of graphene, searching for the applications with zero bandgap has been important and in the other, αMoO3 has not been developed for large-scale growth techniques yet even though the applications are strongly expected to be developed. In this thesis, unconventional CVD graphene electronics and large scale αMoO3 synthesis have been studied for very large scale integration (VLSI). A 512 flexible graphene voltage amplifier array and the highest peak-to-valley current ratio NDR devices emitting green color in graphene nanogap are presented so that large-scale CMOS compatible circuit integration can be available for bio and RF (radio frequency) applications. Having 2.8eV bandgap, a large-scale growth method for αMoO3 is developed for the first time showing ambipolar and memristive behaviors.

For the congestion issue, we found that the existing congestion models will very often over-estimate the congestion at the densely routed regions because real routers will perform rip-up and re-route operations and route the nets with detour to avoid overflow. We propose a 3-step approach that is designed to tackle this problem. It can simulate the global routing, detailed routing and rip-up and re-route process in the real routing procedure. Results show that the prediction accuracy can be improved by 30%. In addition, we have also implemented a routability-driven floorplanner with our congestion model. Results show that the number of un-routable wires can be reduced if the number of overflow tiles can be reduced during floorplanning. Then we studied and developed two post-processing steps to be applied on an interconnect optimized floorplan or placement to further reduce the total wirelength or area. For the wirelength issue, we presented an elegant solution to the cell flipping problem. We presented a detailed study of this cell flipping problem in a placement result to reduce interconnect length. We find the optimal flipping of the cells by formulating the cell flipping problem as a mixed integer linear programming problem to give the shortest total wirelength. In order to reduce the runtime, we proposed a cell orientation fixing step to fix the orientations of some cells. Results show that we can obtain optimal result by solving the mixed integer linear programming problem of the remaining variables directly or the problem can be solved by linear programming such that we can still obtain a result very close to the optimal solution with a much shorter runtime. For area reduction on an interconnect optimized floorplan, we proposed a new approach called deadspace utilization to reduce the total area of an interconnect optimized floorplan by making use of the shape flexibility of some modules. Results show that we can apply this deadspace utilization technique to reduce the area and wirelength of the original floorplan further, subject to the constraint of maintaining the routability and congestion of the original floorplan. / We have studied several interconnect-related optimization problems in floor-planning and placement of VLSI circuits in details. When the number of small logic gates is large in a circuit design, good netlist designs may still result in poor layouts because of various interconnect problems. Most of the problems cannot be fixed manually today because of the incomprehensible circuit complexity. Design automation techniques on interconnect issues in physical design of VLSI circuits becomes indispensable. Recently, congestion minimization and wirelength optimization are two hot topics in interconnect planning. / Sham Chiu Wing. / "March 2006." / Adviser: Young Fung Yu. / Source: Dissertation Abstracts International, Volume: 67-11, Section: B, page: 6634. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2006. / Includes bibliographical references (p. 106-115). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstracts in English and Chinese. / School code: 1307.