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HW/SW Partitioning and Pipelined Scheduling Using Integer Linear ProgrammingChen, Chin-Yang 01 August 2005 (has links)
The primary design goal of many embedded systems for multimedia applications is usually meeting the performance requirement at a minimum cost. In this thesis, we proposed two different ILP based approaches for hardware/software (HW/SW) partitioning and pipelined scheduling of embedded systems for multimedia applications. One ILP approach solves the HW/SW partitioning and pipelined scheduling problem simultaneously. Another ILP approach separates the HW/SW partitioning and pipelined scheduling problem into two phases. The first phase is focusing on the HW/SW partitioning and mapping problem. Second phase is used to solve the pipelined scheduling problem. The two ILP approaches not only partition and map each computation task of a particular multimedia application onto a component of the heterogeneous multiprocessor architecture, but also schedules and pipelines the execution of these computation tasks while considering communication time. For the first ILP model, the objective is to minimize the total component cost and the number of pipeline stages subject to the throughput constraint. In the second ILP approach, the objective of the first phase and second phase is to minimize the total component cost and the number of pipeline stages subject to the throughput constraint, respectively.
Finally, experiments on three real multimedia applications (JPEG Encoder, MP3 Decoder, Wavelet Video Encoder) are used to demonstrate the effectiveness of the proposed approaches.
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Optimal selection of Army military construction projects /Dzwonchyk, James D. January 2002 (has links) (PDF)
Thesis (M.S.)--Naval Postgraduate School, 2002. / Thesis advisor(s): Robert F. Dell, William J. Tarantino, Eva D. Regnier. Includes bibliographical references (p. 45-47). Also available online.
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Optimization model for production and delivery planning in JIT-kanban supply chain systems /Srisawat Supsomboon. January 2002 (has links)
Thesis (Ph. D.)--University of Washington, 2002. / Vita. Includes bibliographical references (leaves 71-75).
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Robust algorithms for area and power optimization of digital integrated circuits under variabilityMani, Murari, 1981- 05 October 2012 (has links)
As device geometries shrink, variability of process parameters becomes pronounced, resulting in a significant impact on the power and timing performance of integrated circuits. Deterministic optimization algorithms for power and area lack capabilities for handling uncertainty, and may lead to over-conservative solutions. As a result, there is an increasing need for statistical algorithms that can take into account the probabilistic nature of process parameters. Statistical optimization techniques however suffer from the limitation of high computational complexity. The objective of this work is to develop efficient algorithms for optimization of area and power under process variability while guaranteeing high yield. The first half of the dissertation focuses on two design-time techniques: (i) a gate sizing approach for area minimization under timing variability; (ii) an algorithm for total power minimization considering variability in timing and power. Design-time methods impose an overhead on each instance of the fabricated chip since they lack the ability to react to the actual conditions on the chip. In the second half of the dissertation we develop joint design-time and post-silicon co-optimization techniques which are superior to design-time only optimization methods. Specifically, we develop (i) a methodology for optimization of leakage power using design-time sizing and post silicon tuning using adaptive body bias; (ii) an optimization technique to minimize the total power of a buffer chain while considering the finite nature of adaptability afforded. The developed algorithms effectively improve the overconservatism of the corner-based deterministic algorithms and permit us to target a specified yield level accurately. As the magnitude of variability increases, it is expected that statistical algorithms will become increasingly important in future technology generations. / text
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ASYMPTOTIC ACCURACY OF PARAMETER IDENTIFICATIONKashper, Arik January 1979 (has links)
No description available.
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An average cost Markov decision process model to decide when to challenge a call in a tennis matchNadimpalli, Vamsi Krishna 16 February 2011 (has links)
In a standard tennis match each player has an unlimited opportunity
to challenge an umpire’s call, but if three incorrect challenges are made in a set he is not allowed to challenge anymore in that set. If the set goes into a tie break the limit on incorrect challenges increases by one. These limited
incorrect challenges are not carried over from one set to another. So this is kind of a limited resource available to the player and if he knows how to use
this resource in a best possible way, there is a scope for increasing his overall chances of winning a match. With the motive of gaining insight on when to challenge a call, we have modeled a single game in a tennis match as a Markov decision process. We have also studied the impact of variables like player’s probability of winning a point, the player’s perception of the challengability
of a call and proportion of challengable calls on the decision making process. / text
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Hierarchical programming and applications to economic policyParraga, Fidel Abraham January 1981 (has links)
No description available.
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TOPOLOGICAL ANALYSIS OF ACTIVE NETWORKS AND THE TREE-FINDING PROBLEMDawson, Darrow Finch, 1931- January 1967 (has links)
No description available.
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Computer-assisted instruction: a simplex algorithm laboratoryLewis, Donavon B., 1935- January 1971 (has links)
No description available.
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Maximum cliques with application to protein structure alignmentStrickland, Dawn Michelle 12 1900 (has links)
No description available.
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