No study has focussed on the longitudinal effect of APOE-ε4 genotype on the logical memory delayed recall total (LDELTOTAL) score in late-onset Alzheimer’s disease (AD). The LDELTOTAL scores were collected at baseline, 12, 24, 36 and 48 months from 382 participants with AD, 503 with cognitive normal (CN), 1293 with mild cognitive impairment (MCI) in the Alzheimer's Disease Neuroimaging Initiative (ADNI). A linear mixed model (LMM) was used to investigate the effect of APOE-ε4 on the longitudinal changes in the LDELTOTAL scores adjusted for age, gender, education and baseline Mini Mental State Examination score. There were significant differences in LDELTOTAL scores among AD, CN, and MCI (P < 0.0001) and among APOE-ε4 alleles at baseline (P < 0.0001). In the multivariable LMM, elders with 75+ years (P = 0.0051), females (P < 0.0001), lower education (P < 0.0001), AD and MCI (both P values < 0.0001) were associated with decreased LDELTOTAL values, while the individuals with 1 or 2 APOE-ε4 allele revealed significantly lower LDELTOTAL scores (both P values <0.0001) compared with individuals without APOE-ε4 allele. Further, APOE-ε4 alleles had significant interactions with four follow-up visits, where all follow-up visits showed significantly higher LDELTOTAL score. In addition, gender showed interaction with age, education and APOE-ε4 with follow-up visits. Our findings provide the first evidence of the effect of APOE-ε4 genotype on the logical memory declines related to AD. Further, APOE-ε4 alleles showed interactions with gender and follow-up visits.

Linear mixed model (LMM) has the advantage of modeling the corelated data. Alzheimer’s disease (AD) is a chronic neurogenerative disease that affects the brain of the subject. No study was found to study the longitudinal effect of apolipoprotein E epsilon 4 (APOE4) genotype on the logical memory test total score in AD. A longitudinal data of 844 with AD, 2167 with cognitive normal (CN), and 4472 with mild cognitive impairment (MCI) participants who underwent logical memory examination test in the Alzheimer's Disease Neuroimaging Initiative (ADNI) were investigated. Episodic memory of the study participants was monitored based on a short story told to the participants and then participants asked to recall what was told. The multivariate LMM was used to determine the longitudinal changes in the logical memory test total score adjusting for age and sex. The Akaike information criterion (AIC) statistic and the Bayesian information criterion (BIC) statistic were used to select the best covariance structure. The repeated measures longitudinal analysis was performed using PROC MIXED in SAS 9.4. Both AIC and BIC statistics favor the unstructured correlated structure (UN). Using a UN model in the LMM, the APOE gene was is significantly associated with logical memory test total score (pUN covariance structure is the best. This study provided the first evidence of the effect of APOE4 genotype on the logical memory related to AD.

Today’s feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at low cost and lower energy consumption. SoCs are complex designs with multiple embedded processors, memory subsystems, and application specific peripherals. The memory architecture of embedded SoCs strongly influences the area, power and performance of the entire system. Further, the memory subsystem constitutes a major part (typically up to 70%) of the silicon area for the current day SoC. The on-chip memory organization of embedded processors varies widely from one SoC to another, depending on the application and market segment for which the SoC is deployed. There is a wide variety of choices available for the embedded designers, starting from simple on-chip SPRAM based architecture to more complex cache-SPRAM based hybrid architecture. The performance of a memory architecture also depends on how the data variables of the application are placed in the memory. There are multiple data layouts for each memory architecture that are efficient from a power and performance viewpoint. Further, the designer would be interested in multiple optimal design points to address various market segments. Hence a memory architecture exploration for an embedded system involves evaluating a large design space in the order of 100,000 of design points and each design points having several tens of thousands of data layouts. Due to its large impact on system performance parameters, the memory architecture is often hand-crafted by experienced designers exploring a very small subset of this design space. The vast memory design space prohibits any possibility for a manual analysis. In this work, we propose an automated framework for on-chip memory architecture exploration. Our proposed framework integrates memory architecture exploration and data layout to search the design space efficiently. While the memory exploration selects specific memory architectures, the data layout efficiently maps the given application on to the memory architecture under consideration and thus helps in evaluating the memory architecture. The proposed memory exploration framework works at both logical and physical memory architecture level. Our work addresses on-chip memory architecture for DSP processors that is organized as multiple memory banks, with each back can be a single/dual port banks and with non-uniform bank sizes. Further, our work also address memory architecture exploration for on-chip memory architectures that is SPRAM and cache based. Our proposed method is based on multi-objective Genetic Algorithm based and outputs several hundred Pareto-optimal design solutions that are interesting from a area, power and performance viewpoints within a few hours of running on a standard desktop configuration.