Furthering our understanding of children's memory mechanisms will expand our knowledge of ways to reduce false memory errors. Hege and Dodson (2004) found that adult participants who studied pictures later recalled items more accurately than participants who studied words. This demonstrated that encoding information in a distinctive manner can reduce false memories. The main aim of the present study was to explore whether using distinctive information within the Deese-Roediger-McDermott paradigm can reduce false memories in children (Deese, 1959; Roediger & McDermott, 1995). Two hundred and forty-three eleven year-old children (mean age 11.5) studied pictures and words on a screen, each with an accompanying aural label. In contrast to the findings of Hege and Dodson, studying pictures did not reduce false memories in these participants. There were no significant encoding differences between children who studied pictures and children who studied words, as measured by the rate of falsely recalled non-presented critical lure words. Moreover, the children's average rate of recall of the false memories was very low (19.6%). This is just over half the rate reported by Hege and Dodson with adult subjects. On the other hand, manipulation of the test instructions at retrieval had a significant effect on the rate of recall of critical lures. Each group of participants received different retrieval instructions. As expected, the highest numbers of recalled critical lures occurred when subjects were asked to report studied items as well as related items (inclusion recall instructions). This study demonstrated the complex role of encoding and retrieval mechanisms in older children's memory processes, and showed that children do not appear to reduce false memories in a manner that is consistent with adults. The results are discussed in terms of children's processing of pictures and words, eleven-year-olds' semantic development, and links to fuzzy-trace theory.

Furthering our understanding of children's memory mechanisms will expand our knowledge of ways to reduce false memory errors. Hege and Dodson (2004) found that adult participants who studied pictures later recalled items more accurately than participants who studied words. This demonstrated that encoding information in a distinctive manner can reduce false memories. The main aim of the present study was to explore whether using distinctive information within the Deese-Roediger-McDermott paradigm can reduce false memories in children (Deese, 1959; Roediger & McDermott, 1995). Two hundred and forty-three eleven year-old children (mean age 11.5) studied pictures and words on a screen, each with an accompanying aural label. In contrast to the findings of Hege and Dodson, studying pictures did not reduce false memories in these participants. There were no significant encoding differences between children who studied pictures and children who studied words, as measured by the rate of falsely recalled non-presented critical lure words. Moreover, the children's average rate of recall of the false memories was very low (19.6%). This is just over half the rate reported by Hege and Dodson with adult subjects. On the other hand, manipulation of the test instructions at retrieval had a significant effect on the rate of recall of critical lures. Each group of participants received different retrieval instructions. As expected, the highest numbers of recalled critical lures occurred when subjects were asked to report studied items as well as related items (inclusion recall instructions). This study demonstrated the complex role of encoding and retrieval mechanisms in older children's memory processes, and showed that children do not appear to reduce false memories in a manner that is consistent with adults. The results are discussed in terms of children's processing of pictures and words, eleven-year-olds' semantic development, and links to fuzzy-trace theory.

Non-volatile memories are an emerging storage technology with wide applica- tions in many important areas. This study focuses on new storage techniques for flash memories and phase-change memories. Flash memories are currently the most widely used type of non-volatile memory, and phase-change memories (PCMs) are the most promising candidate for the next-generation non-volatile memories. Like magnetic recording and optical recording, flash memories and PCMs have their own distinct properties, which introduce very interesting data storage problems. They include error correction, cell programming and other coding problems that affect the reliability and efficiency of data storage. Solutions to these problems can signifi- cantly improve the longevity and performance of the storage systems based on flash memories and PCMs. In this work, we study several new techniques for data storage in flash memories and PCMs. First, we study new types of error-correcting codes for flash memories – called error scrubbing codes –that correct errors by only increasing cell levels. Error scrubbing codes can correct errors without the costly block erasure operations, and we show how they can outperform conventional error-correcting codes. Next, we study the programming strategies for flash memory cells, and present an adaptive algorithm that optimizes the expected precision of cell programming. We then study data storage in PCMs, where thermal interference is a major challenge for data reliability. We present two new coding techniques that reduce thermal interference, and study their storage capacities and code constructions.

Thesis (Ph. D.)--Lehigh University, 2000. / Includes vita. Includes bibliographical references (leaves 145-151).

Ongoing technology improvements and feature size reduction have led to an increase in manufacturing-induced parameter variations. These variations affect various memory cell circuits, making them unreliable at low voltages. Memories are very dense structures that are especially susceptible to defects, and more so at lower voltages. Transient errors due to radiation, power supply noise, etc., can also cause bit-flips in a memory. To protect the data integrity of the memory, an error correcting code (ECC) is generally employed. Present ECC, however, is either single error correcting or corrects multiple errors at the cost of high redundancy or longer correction time. This research addresses the problem of memory reliability under adverse conditions. The goal is to achieve a desired reliability at reduced redundancy while also keeping in check the correction time. Several methods are proposed here including one that makes use of leftover spare columns/rows in memory arrays [Datta 09] and another one that uses memory characterization tests to customize ECC on a chip by chip basis [Datta 10]. The former demonstrates how reusing spare columns leftover from the memory repair process can help increase code reliability while keeping hardware overhead to a minimum. In the latter case customizing ECCs on a chip by chip basis shows considerable reduction in check bit overhead, at the same time providing a desired level of protection for low voltage operations. The customization is done with help from a defect map generated at manufacturing time, which helps identify potentially vulnerable cells at low voltage. An ECC based solution for tackling the wear out problem of phase change memories (PCM) has also been presented here. To handle the problem of gradual wear out and hence increasing defect rates in PCM systems an adaptive error correction scheme is proposed [Datta 11a]. The adaptive scheme, implemented alongside the operating system seeks to increase PCM lifetime by manifold times. Finally the work on memory ECC is extended by proposing a fast burst error correcting code with minimal overhead for handling scenarios where multi-bit failures are common [Datta 11b]. The twofold goal of this work – design a low-cost code capable of handling multi bit errors affecting adjacent cells, and fast multi bit error correction – is achieved by modifying conventional Orthogonal Latin Square codes into burst error codes. / text

Discrete charge-trapping flash memories are more promising than their floating-gate counterparts due to their physically discrete-trapping and coupling-free nature. Si3N4 is conventional material as charge-trapping layer (CTL) for charge storage. The shortcomings of Si3N4 are its low dielectric constant and small barrier height at its interface with SiO2 tunneling layer. Therefore, this research aims to investigate new materials as CTL for improving the performance of the memory devices. The charge-trapping characteristics of La2O3 with and without nitrogen incorporation were investigated. Compared with the memory device with La2O3 as CTL, the one with nitrided La2O3 (LaON) showed larger memory window, higher program/erase (P/E) speeds and smaller charge loss, due to the nitrided La2O3 film exhibiting less crystallized structure, higher trap density induced by nitrogen incorporation, and suppressed leakage by nitrogen passivation. In order to further improve the performance of the memory device with LaON CTL, a device with band-engineered LaTiON/LaON structure as CTL was also explored, and demonstrated to have better performance than the one with LaON CTL. This was ascribed to the variable tunneling path of charge carriers under P/E and retention modes (realized by the band-engineered charge-trapping layer), high trap density of LaTiON, and large barrier height at the LaTiON/SiO interface. SrTiO 3and BaTiO3 ,both ofwhich are typical perovskite-type dielectrics, also possess distinguished characteristics as CTL, including remarkably high dielectric constant and large conduction-band offset relative to SiO2. The charge-trapping properties of SrTiO3 with and without fluorine incorporation were studied. The device with fluorinated SrTiO3 film showed promising performance in terms of higher P/E speeds at a low gate voltage, better endurance and data retention compared with that without fluorine treatment. These advantages were associated with generated deep-level traps, reduced leakage path, and enhanced strength of the film due to the highest electro-negativity of the fluorine atoms incorporated in the film. The charge-trapping properties of BaTiO3 with and without Zr incorporation were also investigated, where Zr incorporated in BaTiO3 could strengthen the dielectric film and improve its thermodynamic stability. The device with Zr incorporation exhibited similar memory window as the one without Zr incorporation, but higher program speed at low gate voltage, better endurance and data retention, due to the Zr-doped BaTiO3 exhibiting higher charge-trapping efficiency and higher density of traps with deeper energy levels. Besides nitride-based memories, nanocrystal-based memories are another type of charge-trapping memories, where nanocrystals (NCs) embedded into a dielectric are used for charge storage. Memory devices with Ga2O3 NCs as CTL were investigated, which are compatible with the CMOS process. The Ga2O3 NCs displayed higher trap density than the Ga2O3 dielectric film. Moreover, compared with the device with Ga2O 3NCs as CTL, the one with nitrided Ga2O3 NCs showed larger memory window, higher operating speed and better data retention, mainly due to higher charge-trapping efficiency of the nitrided Ga2O3 NCs and nitrogen-induced suppressed formation of interlayer at the Ga2O/SiO interface. / published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

Discrete charge-trapping flash memory is being developed for the next-generation commercial flash-memory applications due to its advantages over the traditional floating-gate counterpart. Currently, Si3N4 is widely used as charge-trapping layer (CTL). However, Si3N4 has low dielectric constant and small conduction-band offset with respect to the SiO2 tunneling layer, imposing limitation on further applications. Therefore, this research emphasized on investigating new dielectrics with appropriate fabrication methods to replace Si3N4 as CTL for achieving improved memory performance. Firstly, GeON CTL annealed at different temperatures was investigated. The memory device with post-deposition annealing at 600 0C exhibited the largest memory window, the best charge retention performance, and the highest reliability. These good results are due to the fact that optimal annealing temperature could suppress shallow traps and also produce new traps with desirable energy levels in the CTL. Since ZnON has a negative conduction-band offset (NCBO) with respect to Si, the traps located in the bandgap of ZnON should have deep energy levels. The memory performances of ZrON film with and without Zn doping were studied. Experimental results showed that ZrZnON film had higher program speed and better charge retention performance due to many deeper trap levels induced by the Zn doping, as well as higher erase speed due to the direct recombination of electrons at these deeper trap levels with incoming holes and the intermediary role of these deeper trap levels under erase mode. MoO3 is another NCBO dielectric with a high K value and many oxygen vacancies. La2O3, a rare-earth metal oxide, is a promising dielectric as CTL. To combine the advantages of both La2O3 and MoO3, Mo-doped La2O3 was proposed as a new CTL. Compared to the device with pure La2O3, the one with LaMoO film as CTL had significantly larger C-V hysteresis window, much higher P/E speeds, and better charge retention due to the deeper-level traps and deeper quantum wells created by the LaMoO film. Nitrogen incorporation is a popular approach to increase the trap density in the bulk of CTL. In this research, the memory performances of GdTiO films with and without nitrogen incorporation were compared. Since the nitrogen incorporation induced smaller equivalent oxide thickness, produced nitride-related traps with desirable energy level and larger cross-section for charge capture, the GdTiON film possessed better memory performance than the GdTiO film. Finally, fluorine plasma was employed to improve the quality of blocking layer. The memory device with AlOF blocking layer obtained higher program speed, better reliability and better charge retention than that based on AlO blocking layer. The improved performance was due to the fact that the fluorine incorporation passivated the defects and removed the excess oxygen in the bulk of the blocking layer. In summary, dielectric plays important roles in the performance of charge-trapping flash memory. Memory devices with GeON, ZrZnON, LaMoO, or GdTiON as charge trapping layer and AlOF as blocking layer can produce large memory window, high program/erase speed and good charge retention. / published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

Laboratory methods for studying memory blocking and recovery include directed forgetting, retrieval-induced forgetting, and retrieval bias or memory blocking procedures. These methods primarily use word lists. For example, striking, reversible forgetting effects have been reported for both emotional (e.g., expletives) and non-emotional (e.g., tools) categorized lists of words. The present study examined forgetting and recovery of richer, more episodic materials. Participants studied a series of brief narrative passages varying in emotional intensity, such as a vignette involving torture or child abuse (emotional) vs. vignettes about cycling or insects (non-emotional). Free recall of the 1-word titles of the vignettes (e.g., Torture, Cyclist) showed a strong memory blocking effect, and cues from the stories on a subsequent cued recall test reversed the effect. In a second experiment, vignette-related pictures inserted into an incidental picture naming task triggered some recovery of initially forgotten vignettes, as shown on a post-test. Both emotional and non-emotional stories were susceptible to this reversible memory blocking effect.

TCAD simulations have been performed using SILVACO ATLAS 2D device simulator for a Zero-Capacitor Random Access Memory, a new generation memory cell which is being researched as an alternative for DRAM memory cells in order to get rid of the bulky storage capacitor. In our study we have taken into consideration, a Dual Gate - ZRAM (DGZRAM) as it helps reduce drain-induced barrier lowering and hence leakage, while having better control of the charge in the substrate, The states are written into the device using impact ionization to generate a large number of holes in the substrate, which alter the threshold voltage of the device. The effect of the gate oxide thickness and substrate body thickness are being taken into consideration to increase the change in the threshold voltage and thereby the noise margin. A DGZRAM structure with a Quantum Well introduced into the substrate via a SiGe layer was also simulated. The quantum well introduces a hole storage pocket in the substrate. Comparisons in terms of noise margin, have been made for both the devices which show that the structure with the quantum well in the substrate performs better than the bulk structure. The effect of impact ionization on the electron and hole concentrations have been shown for both the devices. Simulations have been performed taking into consideration gate electrodes with different work functions and it has been observed that while n-polysilicon has a detrimental impact in MOSFETs due to high off-state leakage current, it can be used to obtain low power memory cells. Parameters such as the quantum well doping, composition of Ge in the quantum well, channel length of the device, SiGe layer thickness and its position with respect to the top gate have been varied to obtain the optimum noise margin for the device.

Les implants cardiaques tels que les défibrillateurs implantables sont des appareils permettant de sauver la vie dans le cas de troubles de l’arythmie cardiaque soudaine. Tandis que dans le cas des attaques cardiaques, les implants CRT sont utilisés pour rétablir la cadence de la contraction cardiaque. De tels traitements consistent en l’application de stimulations locales au tissue cardiaque via des électrodes se trouvant dans les sondes de stimulation. Ces dernières se présentent soit dans une configuration unipolaire ou bipolaire qui ont prouvé leur efficacité pour stimuler le ventricule droit et l’oreillette droite ; des études ont montré l’efficacité de la sonde multi-électrode dans la stimulation du ventricule gauche indispensable pour la resynchronisation cardiaque. Cette thèse traite de la conception et l’optimisation d’un système multi-électrodes capable d’éviter les limitations et les contraintes liées à la stimulation du ventricule gauche. Tout d’abord, une réalisation de ce système cette est présentée et fabriqué dans une technologie 0.18 µm. Le circuit a également un protocole de communication spécifique. Il permet une opération basse consommation et une configuration rapide. Ensuite, la conception et la réalisation d’une unité de configuration par défaut est présentée. Cette unité assure la compatibilité de notre sonde avec les stimulateurs cardiaques du marché. Finalement, une étude pour l’adaptation et l’intégration des technologies mémoire non-volatile dans la sonde est présentée. De telles technologies améliorent considérablement le système en évitant le besoin de reconfiguration des sondes et en conséquence réduire la latence et la consommation. / Cardiac implants like ICD are life saving devices for cardiac arrhythmias. In other conditions like heart failure, CRT implants are prescribed to restore the heart rhythm. Such treatment consists of the delivery of electrical stimuli to the cardiac tissue via electrodes in the stimulation lead. Conventionally the stimulation lead come either in unipolar or bipolar configuration which have been found to be sufficient for pacing the right atrium and right ventricle, studies have shown the benefits of a multi-electrode system for pacing left ventricle essential for cardiac resynchronization. This thesis discusses the design and optimization of a multi-electrode system capable of alleviating the limitations and constraints related to left ventricular stimulation. We first present implementation of such system that was taped out in 0.18 µm technology. The chip also features a specially designed communication protocol which enables low power operation and quick configuration. Thereafter we present the design and implementation of a default connection unit to ensure the compatibility of our multi-electrode lead with in the market. This unit was taped out in 0.18 µm technology. Finally we present a proof of concept study for the adaptation and integration of non-volatile memory technologies within the multi-electrode system. The employment of such technologies enhanced our multi-electrode system by eliminating the repetitive configuration of electrodes, thereby saving power and reducing latency. This also included smaller area and compatibility with any pacemaker in the market. Through simulations we proved the feasibility of these technologies for our implant applications.