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The emergence of novel electronic, optical and magnetic properties in ordered two-dimensional (2D) nanoparticle ensembles, due to collective dipolar interactions of surface plasmons or excitons or magnetic moments have motivated intense research efforts into fabricating functional nanostructure assemblies. Such functional assemblies (i.e., highly-integrated and addressable) have great potential in terms of device performance and cost benefits. Presently, there is a paradigm shift from lithography based top-down approaches to bottom-up approaches that use self-assembly to engineer addressable architectures from nanoscale building blocks. The objective of this dissertation was to develop appropriate processing tools that can overcome the common challenges faced in fabricating floating gate memory devices using self-assembled 2D metal nanoparticle arrays as charge storage nodes. The salient challenges being to synthesize monodisperse nanoparticles, develop large scale guided self-assembly processes and to integrate with Complementary Metal Oxide Semiconductor (CMOS) memory device fabrication processes, thereby, meeting the targets of International Technology Roadmap for Semiconductors (ITRS) – 2017, for non-volatile memory devices. In the first part of the thesis, a simple and robust process for the formation of wafer-scale, ordered arrays using dodecanethiol capped gold nanoparticles is reported. Next, the results of ellipsometric measurements to analyze the effect of excess ligand on the self-assembly of dodecanethiol coated gold nanoparticles at the air-water interface are discussed. In a similar vein, the technique of drop-casting colloidal solution is extended for tuning the interparticle spacing in the sub-20 nm regime, by altering the ligand length, through thiol-functionalized polystyrene molecules of different molecular weights. The results of characterization, using the complementary techniques of Atomic Force Microscopy (AFM) and Field-Emission Scanning Electron Microscopy (FESEM), of nanoparticle arrays formed by polystyrene thiol (average molecular weight 20,000 g/mol) grafted gold nanoparticles (7 nm diameter) on three different substrates and also using different solvents is then reported. The substrate interactions were found to affect the interparticle spacing in arrays, changing from 20 nm on silicon to 10 nm on a water surface; whereas, the height of the resultant thin film was found to be independent of substrate used and to correlate only with the hydrodynamic diameter of the polymer grafted nanoparticle in solution. Also, the mechanical properties of the nanoparticle thin films were found to be significantly altered by such compression of the polymer ligands. Based on the experimental data, the interparticle spacing and packing structure in these 2D arrays, were found to be controlled by the substrate, through modulation of the disjoining pressure in the evaporating thin film (van der Waals interaction); and by the solvent used for drop casting, through modulation of the hydrodynamic diameter. This is the first report on the ability to vary interparticle spacing of metal nanoparticle arrays by tuning substrate interactions alone, while maintaining the same ligand structure. A process to fabricate arrays with square packing based on convective shearing at a liquid surface induced by miscibility of colloidal solution with the substrate is proposed. This obviates the need for complex ligands with spatially directed molecular binding properties. Fabrication of 3D aggregates of polymer-nanoparticle composite by manipulating solvent-ligand interactions is also presented. In flash memory devices, charges are stored in a floating gate separated by a tunneling oxide layer from the channel, and the tunneling oxide thickness is scaled down to minimize power consumption. However, reduction in tunneling oxide thickness has reached a stage where data loss can occur due to random defects in the oxide. Using metal nanoparticles as charge-trapping nodes will minimize the data loss and enhance reliability by compartmentalizing the charge storage. In the second part of the thesis, a scalable and CMOS compatible process for fabricating next-generation, non-volatile, flash memory devices using the self-assembled 2D arrays of gold nanoparticles as charge storage nodes were developed. The salient features of the fabricated devices include: (a) reproducible threshold voltage shifts measured from devices spread over cm2 area, (b) excellent retention (>10 years) and endurance characteristics (>10000 Program/Erase cycles). The removal of ligands coating the metal nanoparticles using mild RF plasma etching was found, based on FESEM characterization as well as electrical measurements, to be critical in maintaining both the ordering of the nanoparticles and charge storage capacity. Results of Electrostatic Force Microscope (EFM) measurements are presented, corroborating the need for ligand removal in obtaining reproducible memory characteristics and reducing vertical charge leakage. The effect of interparticle spacing on the memory characteristics of the devices was also studied. Interestingly, the arrays with interparticle spacing of the order of nanoparticle diameter (7 nm) gave rise to the largest memory window, in comparison with arrays with smaller (2 nm) or larger interparticle spacing (20 nm). The effect of interparticle spacing and ligand removal on memory characteristics was found to be independent of different top-oxide deposition processes employed in device fabrication, namely, Radio-frequency magnetron sputtering (RF sputtering), Atomic Layer Deposition (ALD) and electron-beam evaporation. In the final part of the thesis, a facile method for transforming polydisperse citrate capped gold nanoparticles into monodisperse gold nanoparticles through the addition of excess polyethylene glycol (PEG) molecules is presented. A systematic study was conducted in order to understand the role of excess ligand (PEG) in enabling size focusing. The size focusing behavior due to PEG coating of nanoparticles was found to be different for different metals. Unlike the digestive ripening process, the presence of PEG was found to be critical, while the thiol functionalization was not needed. Remarkably, the amount of adsorbed carboxylate-PEG mixture was found to play a key role in this process. The stability of the ordered nanoparticle films under vacuum was also reported. The experimental results of particle ripening draw an analogy with the well-established Pechini process for synthesizing metal oxide nanostructures. The ability to directly self-assemble nanoparticles from the aqueous phase in conjunction with the ability to transfer these arrays to any desired substrate using microcontact printing can foster the development of applications ranging from flexible electronics to sensors. Also, this approach in conjunction with roll-to-roll processing approaches such as doctor-blade casting or convective assembly can aid in realizing the goal of large scale nanostructure fabrication without the utilization of organic solvents.

This thesis is focused on two topics: (i) synthesis and characterization of bilayer graphene and pyrolytic carbon by atmospheric pressure chemical vapor deposition, and (ii) application of graphene in the fabrication of a buckyball memory device. Monolayer and bilayer graphene are semi-metal with zero bandgap. One can induce a bandgap in bilayer graphene by applying a gate voltage in the stacking direction. Thus, bandgap and Fermi level in bilayer graphene can be controlled simultaneously with a double-gate device, making it a useful material for future semiconducting applications. Controlled synthesis of bilayer graphene would be the first step to fabricate bilayer graphene based devices. In this context, we report a uniform and low-defect synthesis of bilayer graphene on evaporated nickel films. Ultra-fast cooling is employed to control the number of layers and sample uniformity. The process is self-limiting, which leads to bilayer graphene synthesis over a wide range of growth-time and precursor flow-rate. Pryolytic carbon is another important carbon nanomaterial, due to its diverse applications in electronic and biomedicalengineering. We employ chemical vapor deposition with ultra-fast cooling technique to synthesize pyrolytic carbon. Furthermore, we elucidate a method to calculate the in-plane crystal size by using Raman spectroscopy. Finally, the use of bilayer graphene in a write-once read-many memory device has been demonstrated. The device showed irreversible switching from low-resistance to high-resistance state, with hysteresis in the transport characteristics. The control sample showed random switching and hysteresis due to electromigration of metal atoms into the active material of the device. We attribute the reliability and performance of the reported device to the ultra-smooth graphene contacts, which additionally inhibits electromigration from the underlying metallic film. Moreover, the memory device showed excellent endurance and retention characteristics.

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The thesis consists of three parts. In the first part, we introduce the notion of device-cache-aware schedulers. Modern disk subsystems have many megabytes of memory for various purposes such as prefetching and caching. Current disk scheduling algorithms make decisions oblivious of the underlying device cache algorithms. In this thesis, we propose a scheduler architecture that is aware of underlying device cache. We also describe how the underlying device cache parameters can be automatically deduced and incorporated into the scheduling algorithm. In this thesis, we have only considered adaptive caching algorithms as modern high end disk subsystems are by default configured to use such algorithms. We implemented a prototype for Linux anticipatory scheduler, where we observed, compared with the anticipatory scheduler, upto 3 times improvement in query execution times with Benchw benchmark and upto 10 percent improvement with Postmark benchmark. The second part deals with implementing cooperative caching for the Redhat Global File System. The Redhat Global File System (GFS) is a clustered shared disk file system. The coordination between multiple accesses is through a lock manager. On a read, a lock on the inode is acquired in shared mode and the data is read from the disk. For a write, an exclusive lock on the inode is acquired and data is written to the disk; this requires all nodes holding the lock to write their dirty buffers/pages to disk and invalidate all the related buffers/pages. A DLM (Distributed Lock Manager) is a module that implements the functions of a lock manager. GFS’s DLM has some support for range locks, although it is not being used by GFS. While it is clear that a data sourced from a memory copy is likely to have lower latency, GFS currently reads from the shared disk after acquiring a lock (just as in other designs such as IBM’s GPFS) rather than from remote memory that just recently had the correct contents. The difficulties are mainly due to the circular relationships that can result between GFS and the generic DLM architecture while integrating DLM locking framework with cooperative caching. For example, the page/buffer cache should be accessible from DLM and yet DLM’s generality has to be preserved. The symmetric nature of DLM (including the SMP concurrency model) makes it even more difficult to understand and integrate cooperative caching into it (note that GPFS has an asymmetrical design). In this thesis, we describe the design of a cooperative caching scheme in GFS. To make it more effective, we also have introduced changes to the locking protocol and DLM to handle range locks more efficiently. Experiments with micro benchmarks on our prototype implementation reveal that, reading from a remote node over gigabit Ethernet can be upto 8 times faster than reading from a enterprise class SCSI disk for random disk reads. Our contributions are an integrated design for cooperative caching and lock manager for GFS, devising a novel method to do interval searches and determining when sequential reads from a remote memory perform better than sequential reads from a disk. The third part deals with selecting a primary network partition in a clustered shared disk system, when node/network failures occur. Clustered shared disk file systems like GFS, GPFS use methods that can fail in case of multiple network partitions and also in case of a 2 node cluster. In this thesis, we give an algorithm for fault-tolerant proactive leader election in asynchronous shared memory systems, and later its formal verification. Roughly speaking, a leader election algorithm is proactive if it can tolerate failure of nodes even after a leader is elected, and (stable) leader election happens periodically. This is needed in systems where a leader is required after every failure to ensure the availability of the system and there might be no explicit events such as messages in the (shared memory) system. Previous algorithms like DiskPaxos are not proactive. In our model, individual nodes can fail and reincarnate at any point in time. Each node has a counter which is incremented every period, which is same across all the nodes (modulo a maximum drift). Different nodes can be in different epochs at the same time. Our algorithm ensures that per epoch there can be at most one leader. So if the counter values of some set of nodes match, then there can be at most one leader among them. If the nodes satisfy certain timeliness constraints, then the leader for the epoch with highest counter also becomes the leader for the next epoch (stable property). Our algorithm uses shared memory proportional to the number of processes, the best possible. We also show how our protocol can be used in clustered shared disk systems to select a primary network partition. We have used the state machine approach to represent our protocol in Isabelle HOL logic system and have proved the safety property of the protocol.