Two recent advances are the primary motivating factors for the research in my dissertation. First, virtualization is no longer confined to the powerful server class machines. It has already been introduced into smart-phones and will be a part of other high-end embedded systems like automobiles in the near future. Second, more and more resource intensive and latency sensitive applications are being used in devices which are rather resource constrained and introducing virtualization into the software stack just exacerbates the resource allocation issue. The focus of my research is on memory management in virtualized environments. Existing memory-management mechanisms were designed for server class machines and their implementations are geared towards the applications running primarily on data centers and cloud setups. In these setups, appropriate load balancing and achieving fair division of resources are the goals and over-provisioning may be the norm. Latency involved in resource management mechanisms may not be a big concern. But in case of smart phones and other hand held devices, applications like media streaming, social-networking are prevalent, which are both resource intensive and latency sensitive. Moreover, the bursty nature of their memory requirement results in spikes in memory needs of the virtual machines. As over provisioning is not an option in these domains, fast and effective (memory) resource management mechanisms are necessary. The overall thesis of my dissertation is: with appropriate design and implementation, it is possible to achieve inter-VM memory management with a latency comparable to the latency involved in intra-VM memory management mechanisms like ‘malloc’. Towards realizing and validating this goal, I have made the following research contributions through my dissertation: (1) I analyzed the memory requirement pattern of prevalent applications, which exhibit bursty behavior and showcased the need for fast memory management mechanisms. (2) I designed and implemented a Coordinated Memory Management mechanism in Xen based virtualized setup, based on the split driver principle (3) I analyzed this mechanism and did a comparative evaluation with parallel memory management mechanisms. (4)I analyzed the extent of interference from the schedulers in the operation of the mechanism and implemented constructs that help in reducing the interference and latency. (5) Based on my analysis, I revised the implementation of the mechanism to one in which Xen hypervisor plays a more significant and active role in the coordination of the mechanism and I did a detailed analysis to showcase the latency improvements due to this design change. (6) In order to validate my hypothesis, I did a comparative analysis of inter-vm and intra-vm memory management mechanisms as final part of my dissertation.

No description available.

Thesis (M.S.)--California Polytechnic State University, 2009. / Title from PDF title page; viewed on June 24, 2009. "June 2009." "In partial fulfillment of the requirements for the degree [of] Master of Science in Computer Science." "Presented to the faculty of California Polytechnic State University, San Luis Obispo." Major professor: Alexander Dekhtyar, Ph.D. Includes bibliographical references (p. 160-193).

Thesis (M. S.)--Computing, Georgia Institute of Technology, 2009. / Committee Chair: Loh, Gabriel H.; Committee Member: Clark, Nathan; Committee Member: Jaleel, Aamer; Committee Member: Kim, Hyesoon; Committee Member: Lee, Hsien-Hsin S.; Committee Member: Prvulovic, Milos.

published_or_final_version / abstract / Computer Science / Doctoral / Doctor of Philosophy

No description available.

by Yung, Chan. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1995. / Includes bibliographical references (leaves 107-110). / Abstract --- p.i / Acknowledgement --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Cache --- p.1 / Chapter 1.1.1 --- Introduction --- p.1 / Chapter 1.1.2 --- Data Prefetching --- p.2 / Chapter 1.2 --- Register --- p.2 / Chapter 1.3 --- Problems and Challenges --- p.3 / Chapter 1.3.1 --- Overhead of registers --- p.3 / Chapter 1.3.2 --- EReg --- p.5 / Chapter 1.4 --- Organization of the Thesis --- p.6 / Chapter 2 --- Previous Studies --- p.8 / Chapter 2.1 --- Introduction --- p.8 / Chapter 2.2 --- Data aliasing --- p.9 / Chapter 2.3 --- Data prefetching --- p.12 / Chapter 2.3.1 --- Introduction --- p.12 / Chapter 2.3.2 --- Hardware Prefetching --- p.12 / Chapter 2.3.3 --- Prefetching with Software Support --- p.13 / Chapter 2.3.4 --- Reducing Cache Pollution --- p.14 / Chapter 3 --- BASIC and ADM Models --- p.15 / Chapter 3.1 --- Introduction of Basic Model --- p.15 / Chapter 3.2 --- Architectural and Operational Detail of Basic Model --- p.18 / Chapter 3.3 --- Discussion --- p.19 / Chapter 3.3.1 --- Implicit Storing --- p.19 / Chapter 3.3.2 --- Associative Logic --- p.22 / Chapter 3.4 --- Example for Basic Model --- p.22 / Chapter 3.5 --- Simulation Results --- p.23 / Chapter 3.6 --- Temporary Storage Problem in Basic Model --- p.29 / Chapter 3.6.1 --- Introduction --- p.29 / Chapter 3.6.2 --- Discussion on the Solutions --- p.31 / Chapter 3.7 --- Introduction of ADM Model --- p.35 / Chapter 3.8 --- Architectural and Operational Detail of ADM Model --- p.37 / Chapter 3.9 --- Discussion --- p.39 / Chapter 3.9.1 --- File Partition --- p.39 / Chapter 3.9.2 --- STORE Instruction --- p.39 / Chapter 3.10 --- Example for ADM Model --- p.40 / Chapter 3.11 --- Simulation Results --- p.40 / Chapter 3.12 --- Temporary storage Problem of ADM Model --- p.46 / Chapter 3.12.1 --- Introduction --- p.46 / Chapter 3.12.2 --- Discussion on the Solutions --- p.46 / Chapter 4 --- ADS Model and ADSM Model --- p.49 / Chapter 4.1 --- Introduction of ADS Model --- p.49 / Chapter 4.2 --- Architectural and Operational Detail of ADS Model --- p.50 / Chapter 4.3 --- Discussion --- p.52 / Chapter 4.3.1 --- Prefetching Priority --- p.52 / Chapter 4.3.2 --- Data Prefetching --- p.53 / Chapter 4.3.3 --- EReg File Splitting --- p.53 / Chapter 4.3.4 --- Compiling Procedure --- p.53 / Chapter 4.4 --- Example for ADS Model --- p.54 / Chapter 4.5 --- Simulation Results --- p.55 / Chapter 4.6 --- Discussion on the Architectural and Operational Variations for ADS Model --- p.62 / Chapter 4.6.1 --- Temporary storage Problem --- p.62 / Chapter 4.6.2 --- Operational variation for Data Prefetching --- p.63 / Chapter 4.7 --- Introduction of ADSM Model --- p.64 / Chapter 4.8 --- Architectural and Operational Detail of ADSM Model --- p.65 / Chapter 4.9 --- Discussion --- p.67 / Chapter 4.10 --- Example for ADSM Model --- p.67 / Chapter 4.11 --- Simulation Results --- p.68 / Chapter 4.12 --- Discussion on the Architectural and Operational Variations for ADSM Model --- p.71 / Chapter 4.12.1 --- Temporary storage Problem --- p.71 / Chapter 4.12.2 --- Operational variation for Data Prefetching --- p.73 / Chapter 5 --- IADSM Model and IADSMC&IDLC Model --- p.75 / Chapter 5.1 --- Introduction of IADSM Model --- p.75 / Chapter 5.2 --- Architectural and Operational Detail of IADSM Model --- p.76 / Chapter 5.3 --- Discussion --- p.79 / Chapter 5.3.1 --- Implicit Loading --- p.79 / Chapter 5.3.2 --- Compiling Procedure --- p.81 / Chapter 5.4 --- Example for IADSM Model --- p.81 / Chapter 5.5 --- Simulation Results --- p.84 / Chapter 5.6 --- Temporary Storage Problem of IADSM Model --- p.87 / Chapter 5.7 --- Introduction of IADSMC&IDLC Model..........: --- p.88 / Chapter 5.8 --- Architectural and Operational Detail of IADSMC & IDLC Model --- p.89 / Chapter 5.9 --- Discussion --- p.90 / Chapter 5.9.1 --- Additional Operations --- p.90 / Chapter 5.9.2 --- Compiling Procedure --- p.93 / Chapter 5.10 --- Example for IADSMC&IDLC Model --- p.93 / Chapter 5.11 --- Simulation Results --- p.94 / Chapter 5.12 --- Temporary Storage Problem of IADSMC&IDLC Model --- p.96 / Chapter 6 --- Compiler and Memory System Support for EReg --- p.99 / Chapter 6.1 --- Impact on Compiler --- p.99 / Chapter 6.1.1 --- Register Usage --- p.99 / Chapter 6.1.2 --- Effect of Unrolling --- p.100 / Chapter 6.1.3 --- Code Scheduling Algorithm --- p.101 / Chapter 6.2 --- Impact on Memory System --- p.102 / Chapter 6.2.1 --- Memory Bottleneck --- p.102 / Chapter 6.2.2 --- Size of EReg Files --- p.103 / Chapter 7 --- Conclusions --- p.104 / Chapter 7.1 --- Summary --- p.104 / Chapter 7.2 --- Future Research --- p.105 / Bibliography --- p.107 / Chapter A --- Source code of the Kernels --- p.111 / Chapter B --- Program Analysis --- p.126 / Chapter B.1 --- Program analysed by Basic Model --- p.126 / Chapter B.2 --- Program analysed by ADM Model --- p.133 / Chapter B.3 --- Program analysed by ADS Model --- p.140 / Chapter B.4 --- Program analysed by ADSM Model --- p.148 / Chapter B.5 --- Program analysed by IADSM Model --- p.156 / Chapter B.6 --- Program analysed by IADSMC&IDLC Model --- p.163 / Chapter C --- Cache Simulation on Prefetching of ADS model --- p.174

We present a type-based approach to statically derive symbolic closed-form formulae that characterize the bounds of heap memory usages of programs written in object-oriented languages. Given a program with size and alias annotations, our inference system will compute the amount of memory required by the methods to execute successfully as well as the amount of memory released when methods return. The obtained analysis results are useful for networked devices with limited computational resources as well as embedded software. / Singapore-MIT Alliance (SMA)

In this thesis, we integrate the memory subsystem, including cache and MMU¡]Memory Management Unit¡^ with the embedded 32 bits microprocessor SYS32TM-II to support the virtual memory mechanism of the operating system and make memory management effectively among multi-processes in the system. To provide the virtual to physical address translation with MMU and to improve the system performance with cache. We reuse the memory subsystem of the LEON2 SoC platform and design the communication interface to coordinate the processor core SYS32TM-II with the LEON2 memory subsystem, and modify the LEON2 memory subsystem to compatible with SYS32TM-II. After the integration of memory subsystem, a reusing cache for program address trace compression in real time is proposed. The advantage is that reusing cache with minor hardware modification can not only save the hardware compressor overhead but also obtain a high compression ratio. Experimental results show that the proposed approach causes few hardware area overhead but achieves approximately 90% compression ratio at real-time. Therefore, this thesis is the memory subsystem with parameterized design and with the ability to support system debugging. The role of the memory subsystem is not only to improve the system performance and to provide the hardware support requiring by the operating system, with minor modification, the memory susbsystem can also capture the dynamic program execution trace in parallel with microprocessor. The address trace compression mechanism will not effect the program execution and capable to compress at real-time.

Thesis (Ph. D.)--University of Washington, 2000. / Vita. Includes bibliographical references (leaves 128-131).