Along with process technology advancement, we can integrate more and more on-chip memory in an SOC. Memory intensive applications, such as image processing and digital signal processing, usually access certain number of data arrays. Memory system designs for such systems can then critically influence cost, performance, and power of the resulting SOCs. In this thesis research, we focus on the software design of a memory synthesis method of data stored in arrays. Memory synthesis task considers access time, power, and cost requirements of array data and utilize characteristics of indexing patterns of array accesses. It then derive the allocation of memory organizations and effective organizations of multiple data arrays mapped onto the allocated memory modules. Its design principle lies in the matching of data array reorganization and their assigned memory module resource allocation so as to enhance data access locality in the same memory rows and to reduce the number of row accesses (bit line accesses). Hence, we can achieve required power and performance goals with low memory system cost. Static memory synthesis solves memory synthesis problem with fixed loop count and tasks in prior of product design. The memory synthesis task succeeds the high level synthesis task. It is then followed by the address generating circuit design task and the memory access scheduling circuit design task of the functional module side. These circuit designs can herein be combined with high level synthesis results to perform logic synthesis. Finally, we can perform physical synthesis of functional modules, logic circuit modules, and memory modules. It is thus expected to produce an SOC design satisfying overall design requirements. The software design of the static memory synthesis method includes two main topics: memory allocation and module assignment for data arrays and the estimation method of a memory system design. In this research, we designed the experimental software for the memory synthesis method. We also planned experiments based upon real and synthetic design cases to validate the effectiveness of the static memory synthesis method.

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Cubic-phase silicon carbide (andamp;acirc;-SiC) nanostructures were successfully synthesized by the reaction of silicon monoxide (SiO) powder with multi-walled carbon nanotubes (MWCNTs) at high temperatures. Experiments were conducted under vacuum or in the presence of argon gas in a high-temperature furnace and the fabrication parameters of temperature (1300 -1500andamp;deg;C), time, and reactant material mass were varied to optimize the material. The resulting samples were then physically characterized using X-ray diffraction (XRD), scanning electron microscopy (SEM) and transmission electron microscopy (TEM). XRD analysis revealed the presence of dominant andamp;acirc;-silicon carbide phases. SEM images depicted morphologies similar to the starting MWCNTs, having relatively larger diameter sizes, shorter lengths and reduced curvature. TEM observations showed the presence of solid and hollow nanostructures with both crystalline and amorphous regions. Additional experiments were performed to investigate de-aggregation and dispersion procedures for the andamp;acirc;-SiC nanostructures fabricated. Optimum results for these experiments were achieved by ultrasonication of 0.01 wt.% andamp;acirc;-SiC in N,N dimethyl formamide (DMF) and dispersion using a spin coater. A methodology for electrical testing of andamp;acirc;-SiC nanostructures was developed using the de-aggregation and dispersion process established. SEM observations revealed that the random nature of the dispersion procedure used was not efficient in forming contacts regions that would allow electrical measurements of andamp;acirc;-SiC nanostructures on the pre-patterned silicon substrate.