<p> </p><p>The deep sub micron process technology and application convergence increases the design challenges in System-on-Chip (SoC). The traditional bus based on chip communication are not scalable and fails to deliver the performance requirements of the complex SoC. The Network on Chip (NoC) has been emerged as a solution to address these complexities of a efficient, high performance, scalable SoC design. The Aethereal NoC provides the latency and throughput bounds by pipelined timedivision multiplexed (TDM) circuit switching architecture. A global synchronous clock defines the timing for TDM, which is not beneficial for decreasing process geometry and increasing clock frequency. This thesis work focuses on the Aelite NoC architecture. The Aelite NoC offering guaranteed services exploits the complexities of System-on-Chip design with real time requirements. The Aelite NoC implements flit synchronous communication using mesochronous and asynchronous links.</p><p> </p><p> </p>

The deep sub micron process technology and application convergence increases the design challenges in System-on-Chip (SoC). The traditional bus based on chip communication are not scalable and fails to deliver the performance requirements of the complex SoC. The Network on Chip (NoC) has been emerged as a solution to address these complexities of a efficient, high performance, scalable SoC design. The Aethereal NoC provides the latency and throughput bounds by pipelined timedivision multiplexed (TDM) circuit switching architecture. A global synchronous clock defines the timing for TDM, which is not beneficial for decreasing process geometry and increasing clock frequency. This thesis work focuses on the Aelite NoC architecture. The Aelite NoC offering guaranteed services exploits the complexities of System-on-Chip design with real time requirements. The Aelite NoC implements flit synchronous communication using mesochronous and asynchronous links.

<p>All large-scale digital Integrated Circuits need an appropriate strategy for clocking and synchronization. In large-scale and high-speed System-on-Chips (SoC), the traditional"Globally Synchronous"(GS) approach is not longer viable, due to severe wire delays. Instead new solutions as"Globally Synchronous, Locally Asynchronous"(GALS) approaches have been proposed. We propose to replace the GALS approach with a mesochronous clocking principle. In this work, such an approach together with a circuit solution in 0.18mm CMOS process has been presented. This solution allows clocking frequencies up to 4 GHz.</p>

All large-scale digital Integrated Circuits need an appropriate strategy for clocking and synchronization. In large-scale and high-speed System-on-Chips (SoC), the traditional"Globally Synchronous"(GS) approach is not longer viable, due to severe wire delays. Instead new solutions as"Globally Synchronous, Locally Asynchronous"(GALS) approaches have been proposed. We propose to replace the GALS approach with a mesochronous clocking principle. In this work, such an approach together with a circuit solution in 0.18mm CMOS process has been presented. This solution allows clocking frequencies up to 4 GHz.

Dr. Paul V. Gratz Network-on-Chip (NoC) designs have emerged as a replacement for traditional shared-bus designs for on-chip communications. As with all current VLSI design, however, reducing power consumption in NoCs is a critical challenge. One approach to reduce power is to dynamically scale the voltage and frequency of each network node or groups of nodes (DVFS). Another approach to reduce power consumption is to replace the balanced clock tree with a globally-asynchronous, locally-synchronous (GALS) clocking scheme. NoCs implemented with either of these schemes, however, tend to have high latencies as packets must be synchronized at the intermediate nodes between source and destination. In this work, we propose a novel router microarchitecture which offers superior performance versus typical synchroniz- ing router designs. Our approach features Asynchronous Bypass Channels (ABCs) at intermediate nodes thus avoiding synchronization delay. We also propose a new network topology and routing algorithm that leverage the advantages of the bypass channel offered by our router design. Our experiments show that our design improves the performance of a conventional synchronizing design with similar resources by up to 26 percent at low loads and increases saturation throughput by up to 50 percent.