Although computers have long been studied in terms of their changing price/performance ratio, the issue of accounting for performance in computer systems has not been adequately addressed. This paper addresses the topic in three ways. First, a survey of IS Managers and business "power-users" of personal computers was conducted to empirically determine the attributes of computer systems that provide value to users; these results guide subsequent choices regarding the operationalisation of user value. Second, an index of system performance was developed from published performance benchmarks and used as a direct measure of performance in the hedonic function. Third, a set of technical proxies was shown to adequately reproduce the performance index derived above, and was used in an alternate specification of the hedonic function. Using data on IBM-PC compatible laptop and desktop systems, price indexes were constructed using both approaches to performance measurement. The results demonstrated that both approaches yielded good explanatory power and nearly identical estimates of the rate of quality adjusted price change in PC systems. Thus, the set of technical proxies could be used to operationalise performance in a larger data set for which direct performance measures are unavailable. For the 1990s, laptop PCs were found to have decreased in quality adjusted price at an average of 39% per year while the corresponding figure for desktop PCs was 35% per year. / Business, Sauder School of / Graduate

Research Report submitted to the Faculty of Science, University of the Witwatersrand, Johannesburg, towards a partial fulfilment of the requirements for the degree of Master of Science Johannesburg 1991 / This report describes and evaluates an implementation of the Linda tuple space abstraction on Transputer networks. There is evidence that suggests a need for a new programming methodology to support Transputer-based applications, and Linda, as an attractive and elegant alternative to existing methodologies, has great potential for this role. The research focuses on the implementation of a particular tuple space model, intermediate uniform distribution, on Transputer meshes. The objective of the research is to ascertain the extent of the communication overheads inherent in the implementation and hence evaluate the feasibility of the approach. The overheads are measured relative to message passing performance on native Transputer networks, and are shown to be significant. It is concluded that although the specific tuple space model is not ideally suited to Transputer-based systems and the implementation, as it stands, is too inefficient to be of practical use, the approach requires further exploration in order to exhaust its full research potential. / MT2017

Thesis (M.B.A.)--University of Hong Kong, 1984.

Thesis (M.S.)--Ohio University, August, 1982. / Title from PDF t.p.

Thesis (M.S.)--University of Wisconsin--Madison, 1984. / Typescript. eContent provider-neutral record in process. Description based on print version record. Includes bibliographical references (leaves 106-110).

Thesis (M.S.)--University of Wisconsin--Madison, 1981. / Typescript. eContent provider-neutral record in process. Description based on print version record.

Thesis (M.S.)--University of Wisconsin--Madison, 1980. / Typescript. eContent provider-neutral record in process. Description based on print version record. Includes bibliographical references (leaves 56-57).

This thesis describes the operation of an intelligent controller existing between a computer system and a peripheral. The intelligent controller is implemented with an INTEL universal peripheral interface, UPI-41, single chip slave microcomputer. The interfaces between the controller and the computer system, and the controller and the peripheral are described in detail, as are the firmware and internal facilities of the controller itself. An evaluation of system operation is presented and, finally, the organizational philosophy of the system is discussed. Located within the appendices are a system schematic and listing of the controller program.

Two candidate microprocessors are selected to demonstrate that microprocessors can be effectively utilized in digital control applications. The Intel 8085A-2 is selected to represent 8-bit microprocessors and the Intel 8086 is selected to represent 16-bit. A baseline second order digital filter algorithm is developed for comparison of the performance of the two microprocessors for both software and hardware multiply implementations. Emulation techniques are utilized to facilitate performance comparison, without large investments in software and hardware development. In addition, they provide a method for evaluating new microprocessors, before hardware becomes available. The emulations are then used to verify and to determine the sampling frequency realizable with each digital filter implementation.

Thesis (Ph. D.)--University of Texas at Austin, 2007. / Vita. Includes bibliographical references.