En campo de redes de comunicaciones y los conmutadores ATM (Asynchronous Transfer Mode), la QoS (Quality of Service) es un aspecto crucial para la gestión del tráfico. El problema de la QoS actualmente es un desafío para los diseñadores, concretamente la implementación eficiente del subsistema QoS e igualmente superar o minimizar los problemas que presenta el empleo de circuitos síncronos.La presente tesis tiene dos vertientes principales: los circuitos asíncronos y la problemática de la QoS para el protocolo de comunicaciones ATM. La tesis se centra en la investigación de una técnica de diseño asíncrona, lo cual implica la eliminación del reloj global, y que facilite la implementación de arquitecturas que eviten o al menos minimicen los problemas encontrados en los equivalentes circuitos síncronos como alineamiento de fase, sincronización, skew y jitter.Dentro de los objetivos principales de la tesis se establece una metodología de diseño asíncrono independiente de la tecnología, y como circuito demostrador se aborda la implementación asíncrona de la Unidad de Clasificación que es el subsistema principal en la gestión QoS-ATM. Se utiliza el estilo de diseño micropipeline que, además de otras ventajas intrínsecas, permite un adecuado balance de la relación área/velocidad y facilidades para test. La arquitectura implementada en FPGA permite satisfacer los requerimientos de throughput y latencia de las normas de transmisión OC-12 (622 Mbits/seg) y OC-48 (2.5 Gbits/seg). / In ATM (Asynchronous Transfer Mode) packet switching, a key point for traffic management is the QoS (Quality of Services) guarantees. Efficient implementation of a QoS sub-system remains a challenge for network designers, equally, designers have to deal with problems in the use of synchronous circuits.The present thesis has two main aspects of research: Asynchronous circuits and the QoS for ATM protocol. In this research, a new approach is the use of an asynchronous technique and elimination of the global clock, it allows the implementation of architectures that can avoid design problems commonly found in their synchronous counterpart. As a consequence, the asynchronous implementation of some blocks in ATM protocol as the QoS sub-system, apart from other intrinsic advantages, it can avoid or at least minimise jitter, skew and synchronisation problems.The main objective of this thesis is to propose a methodology of design technologically independent and as demonstrator circuit; the implementation of a novel asynchronous micropipeline of a Sorter Unit which is the main sub-system for QoS-ATM management. The micropipeline architecture, apart from other intrinsic advantages, it has a good performance in area/speed ratio and easy testability. The prototype is mapped on commercial FPGA and it can meet the QoS-ATM requirements of throughput and latency for OC-12 (622 Mbits/sec) and OC-48 (2.5 Gbits/sec) transmission.

Field Programmable Gate Arrays (FPGAs) are widely used in prototyping digital circuits. However commercial FPGAs are not very suitable for asynchronous design. Both the architecture of the FPGAs and the synthesis tools are mostly tailored to synchronous design. Therefore potential advantages of the asynchronous circuits could not be observed when they are implemented on commercial FPGAs. This is shown by designing an asynchronous arithmetic logic unit (ALU), implemented in the style of micropipelines, on the Xilinx Virtex XCV300 FPGA family. The hazard characteristics of the target FPGA have been analyzed and a methodology for selftimed asynchronous circuits has been proposed. The design methodology proposes first designing a hazard-free cell set, and then using relationally placed macros (RPMs) to keep the hazard-free behavior, and incremental design technique to combine modules in upper levels without disturbing their timing characteristics. The performance of the asynchronous ALU has been evaluated in terms of the logic slices occupied in the FPGA and data latencies, and a comparison is made with a synchronous ALU designed on the same FPGA.