• Refine Query
  • Source
  • Publication year
  • to
  • Language
  • 195
  • 47
  • 19
  • 10
  • 10
  • 10
  • 10
  • 10
  • 10
  • 5
  • 4
  • 2
  • 1
  • 1
  • 1
  • Tagged with
  • 323
  • 136
  • 69
  • 66
  • 51
  • 49
  • 44
  • 38
  • 34
  • 32
  • 31
  • 29
  • 29
  • 28
  • 25
  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

A shared memory multi-microprocessor system with hardware supported message passing mechanisms.

January 1990 (has links)
by Lam Chin Hung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1990. / Bibliography: leaves 167-174. / ABSTRACT --- p.1 / ACKNOWLEDGEMENTS --- p.2 / TABLE OF CONTENTS --- p.3 / Chapter CHAPTER 1 --- INTRODUCTION --- p.1 / Chapter 1.1 --- Gaining performance with multiprocessing --- p.1 / Chapter 1.1.1 --- Software approach --- p.2 / Chapter 1.1.2 --- hardware approach --- p.2 / Chapter 1.2 --- Parallel processing --- p.4 / Chapter 1.3 --- Gaining performance with multiprocessing --- p.7 / Chapter 1.3.1 --- Multiprocessor configurations --- p.7 / Chapter 1.3.2 --- Multiprocessor design issues --- p.9 / Chapter 1.3.3 --- Using microprocessors --- p.11 / Chapter 1.3.4 --- Bus based systems --- p.12 / Chapter 1.4 --- Shared memory and message passing --- p.13 / Chapter 1.4.1 --- Shared memory --- p.13 / Chapter 1.4.2 --- Message passing --- p.14 / Chapter 1.4.3 --- Comparisons of the two paradigms --- p.16 / Chapter 1.5 --- Summary and comment --- p.19 / Chapter CHAPTER 2 --- AN OVERVIEW OF COMMON APPROACHES --- p.20 / Chapter 2.1 --- SUPRENUM --- p.20 / Chapter 2.2 --- MEMSY --- p.22 / Chapter 2.3 --- ELXSI --- p.24 / Chapter 2.4 --- Sequent --- p.25 / Chapter 2.5 --- YACKOS --- p.26 / Chapter 2.6 --- Summary --- p.30 / Chapter CHAPTER 3 --- THE MPC APPROACH --- p.32 / Chapter 3.1 --- A shared memory multiprocessor architecture --- p.32 / Chapter 3.2 --- Message passer for inter-process communication --- p.32 / Chapter 3.2.1 --- A review of the message passer approach --- p.33 / Chapter 3.2.2 --- Pit-falls of the message passer approach --- p.34 / Chapter 3.3 --- The role of the MPC --- p.35 / Chapter 3.3.1 --- The quest for the MPC --- p.35 / Chapter 3.3.2 --- Duties of the MPC --- p.37 / Chapter 3.3.2.1 --- Software aspects --- p.37 / Chapter 3.3.2.2 --- Hardware aspects --- p.40 / Chapter 3.4 --- Advantages and disadvantages --- p.41 / Chapter 3.4.1 --- Advantages --- p.41 / Chapter 3.4.2 --- Disadvantages --- p.43 / Chapter 3.4.3 --- Other discussions --- p.44 / Chapter 3.5 --- Summary --- p.44 / Chapter CHAPTER 4 --- THE DESIGN OF SM3 --- p.46 / Chapter 4.1 --- Introduction to SM3 --- p.45 / Chapter 4.2 --- Software aspects --- p.47 / Chapter 4.2.1 --- Programming model --- p.48 / Chapter 4.2.1.1 --- Logical entities --- p.48 / Chapter 4.2.1.2 --- Communication procedure --- p.48 / Chapter 4.2.2 --- Message structure --- p.51 / Chapter 4.2.2.1 --- Broadcast versus point-to-point messages --- p.52 / Chapter 4.2.2.2 --- Message priority --- p.52 / Chapter 4.2.2.3 --- Blocking versus non-blocking --- p.53 / Chapter 4.3 --- Hardware aspects --- p.55 / Chapter 4.3.1 --- Overall architecture --- p.55 / Chapter 4.3.2 --- The host machine / Chapter 4.3.3 --- Slave processor nodes --- p.57 / Chapter 4.3.4 --- The MPC --- p.59 / Chapter 4.4 --- Communication protocols --- p.60 / Chapter 4.4.1 --- Short and long messages --- p.60 / Chapter 4.4.2 --- Point-to-point messages --- p.61 / Chapter 4.4.3 --- 1-to-N DMA for broadcast messages --- p.63 / Chapter 4.4.3.1 --- Introducing 1-to-N DMA --- p.63 / Chapter 4.4.3.2 --- 1-to-N DMA operation --- p.64 / Chapter 4.4.3.3 --- Merits and demerits of 1-to-N DMA --- p.67 / Chapter 4.5 --- Summary --- p.68 / Chapter CHAPTER 5 --- IMPLEMENTATION ISSUES OF SM3 --- p.70 / Chapter 5.1 --- The shared bus - VMEbus --- p.70 / Chapter 5.1.1 --- Why VMEbus --- p.70 / Chapter 5.1.2 --- Customizing the VMEbus --- p.71 / Chapter 5.2 --- The host machine --- p.71 / Chapter 5.3 --- Slave processor nodes --- p.72 / Chapter 5.3.1 --- Overview of a PN --- p.74 / Chapter 5.3.2 --- The MC68030 microprocessor --- p.77 / Chapter 5.3.3 --- The DMAC M68442 --- p.78 / Chapter 5.3.4 --- Registers --- p.79 / Chapter 5.3.5 --- Shared-bus interface --- p.80 / Chapter 5.3.6 --- Communication logic --- p.80 / Chapter 5.4 --- The MPC --- p.80 / Chapter 5.4.1 --- Overview of the MPC --- p.81 / Chapter 5.4.2 --- Registers --- p.81 / Chapter 5.4.3 --- Communication logic --- p.83 / Chapter 5.5 --- Protocol implementation --- p.84 / Chapter 5.5.1 --- Point-to-point messages --- p.84 / Chapter 5.5.2 --- Broadcast messages --- p.86 / Chapter 5.5.2.1 --- Circular buffer queue --- p.87 / Chapter 5.5.2.2 --- Participating entities --- p.87 / Chapter 5.5.2.3 --- Protocol details --- p.88 / Chapter 5.6 --- System start-up procedure --- p.94 / Chapter 5.6.1 --- Power up reset of PNs --- p.94 / Chapter 5.6.2 --- Initialization of the processor pool --- p.95 / Chapter 5.7 --- Summary --- p.95 / Chapter CHAPTER 6 --- APPLICATION EXAMPLES --- p.96 / Chapter 6.1 --- Introduction --- p.96 / Chapter 6.2 --- Matrix Multiplication --- p.96 / Chapter 6.3 --- Parallel Quicksort --- p.97 / Chapter 6.4 --- Pipeline Problems --- p.99 / Chapter CHAPTER 7 --- UNSOLVED PROBLEMS AND FUTURE DEVELOPMENT --- p.101 / Chapter 7.1 --- Current Status --- p.101 / Chapter 7.2 --- Possible immediate enhancements --- p.102 / Chapter 7.2.1 --- Enhancement to the PNs --- p.102 / Chapter 7.2.2 --- Enhancement of the MPC --- p.103 / Chapter 7.2.3 --- Communication kernel enhancement --- p.103 / Chapter 7.3 --- Limitation of a shared bus --- p.104 / Chapter 7.4 --- Number crunching capability --- p.105 / Chapter 7.5 --- Parallel programming environment --- p.105 / Chapter 7.5.1 --- Conform to serial language --- p.105 / Chapter 7.5.2 --- Moving to parallel programming languages --- p.106 / Chapter 7.5.2.1 --- Uni-processor Unix --- p.107 / Chapter 7.5.2.2 --- Porting Unix --- p.108 / Chapter 7.5.2.3 --- Multiprocessor Unix --- p.108 / Chapter 7.5.3 --- Object-oriented approach --- p.110 / Chapter 7.6 --- Summary --- p.112 / Chapter CHAPTER 8 --- CONCLUSION --- p.113 / Chapter 8.1 --- Thesis summary --- p.113 / Chapter 8.2 --- Author's comment --- p.114 / Chapter 8.3 --- Looking into the future --- p.116 / Chapter APPENDIX A --- BLOCK DIAGRAM --- p.117 / Chapter APPENDIX B --- CIRCUIT DIAGRAMS --- p.119 / Chapter APPENDIX C --- PCB LAYOUT --- p.126 / Chapter APPENDIX D --- VMEBUS ADDRESS MAP --- p.132 / Chapter APPENDIX E --- PROCESSOR NODE ADDRESS MAP --- p.133 / Chapter APPENDIX F --- REGISTER LAYOUT --- p.134 / Chapter F.1 --- Registers on a PN --- p.134 / Chapter F.2 --- Registers on the MPC --- p.134 / Chapter APPENDIX G --- PAL DESIGN --- p.136 / Chapter APPENDIX H --- COMMUNICATION SUB-BUS --- p.146 / Chapter H.1 --- Signal definition --- p.146 / Chapter H.2 --- Pin assignment --- p.146 / Chapter APPENDIX I --- FEASIBILITY OF TASK DISTRIBUTION PLAN --- p.147 / Chapter APPENDIX J --- COMMUNICATION PRIMITIVES --- p.148 / Chapter APPENDIX K --- PHOTOGRAPHS OF SM3 --- p.150 / Chapter APPENDIX L --- PROTOCOL STATE DIAGRAMS --- p.152 / Chapter L.1 --- Predefined partial state diagrams --- p.152 / Chapter L.2 --- Point-to-point messages --- p.152 / Chapter L.3 --- Broadcast messages --- p.154 / Chapter APPENDIX M --- BOOT-UP PROCEDURE OF SM3 --- p.159 / PUBLICATIONS --- p.161 / REFERENCES --- p.162
2

Test generation for realistic defects

Krishnamachary, Arun. Abraham, Jacob A. January 2003 (has links) (PDF)
Thesis (Ph. D.)--University of Texas at Austin, 2003. / Supervisor: Jacob. A. Abraham. Vita. Includes bibliographical references. Available also from UMI Company.
3

A design validation methodology for high performance microprocessors

Krishnamurthy, Narayanan. Abraham, Jacob A., January 2003 (has links) (PDF)
Thesis (Ph. D.)--University of Texas at Austin, 2003. / Supervisor: Jacob A. Abraham. Vita. Includes bibliographical references. Available also from UMI Company.
4

Design language users manual for a microprocessor

Masud, Manzer, 1950- January 1976 (has links)
No description available.
5

Design of a real-time multi-channel microprocessor based data acquisition and control system

Hadi, Muntasir J. January 1988 (has links)
Thesis (M.S.)--Ohio University, November, 1988. / Title from PDF t.p.
6

A hardware-software processor architecture using pipeline stalls for leakage power management

Sheth, Khushbooben. Agrawal, Vishwani D., January 2009 (has links)
Thesis--Auburn University, 2009. / Abstract. Vita. Includes bibliographical references (p. 88-95).
7

Efficient adaptation of multiple microprocessor resources for energy reduction using dynamic optimization

Hu, Shiwen, January 1900 (has links) (PDF)
Thesis (Ph. D.)--University of Texas at Austin, 2005. / Vita. Includes bibliographical references.
8

Test generation for realistic defects

Krishnamachary, Arun 28 August 2008 (has links)
Not available / text
9

A generic system simulator with novel on-chip cache and throughput models for gigascale integration

Eble, John C., III 12 1900 (has links)
No description available.
10

6800 microprocessor system for an enlarging photometer and timer

Torres P., Edgar P. January 1980 (has links)
Thesis (M.S.)--Ohio University, November, 1980. / Title from PDF t.p.

Page generated in 0.0815 seconds