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This thesis presents novel aspects of the design of Strategist, a microprocessor designed to support efficient rewriting-based computation and pattern matching in particular. After introducing the architecture of Strategist, three of its novel features are described: predicate compression, quadrature low-swing logic and a high radix, bufferless on-chip network design. Predicate compression allows processors which make use of predicated execution to save a significant amount of code space, issue bandwidth and energy, by compressing predicate register references in a way that makes use of their peculiar temporal distributions. Quadrature low-swing logic is a new logic style which allows significant improvements in efficiency for realising both simple and complex logic functions in modern semiconductor processes. Finally, we describe a high radix on-chip network design which allows low-latency communication to be sustained under high traffic loads despite its simple, bufferless routers. Taken together, these features enable the design of more efficient special purpose multi-core processors, such as Strategist.

Thesis (Ph. D.)--University of Texas at Austin, 2007. / Vita. Includes bibliographical references.

Thesis (M.S.)--State University of New York at Binghamton, Dept. of Mechanical Engineering, 2007. / Includes bibliographical references.

Thesis (M.S.)--Ohio University, June, 1980. / Title from PDF t.p.

Thesis (M.S.)--Ohio University, August, 1981. / Title from PDF t.p.

Thesis (M.S.)--Ohio University, June, 1983. / Title from PDF t.p.

Thesis (M.S.)--Ohio University, June, 1983. / Title from PDF t.p.

Thesis (M.S.)--Ohio University, March, 1985. / Title from PDF t.p.

Thesis (M.Eng.Sc.) - Dept. of Electrical Engineering, University of Adelaide. / Typescript (photocopy).