Future high-capacity wireless communications will extensively use the broad bands still available millimeter-wave frequencies. Channels with bandwidth broader than those in use today will guarantee enhanced data-rate and reduced latency performance. The recent progress of integrated-circuit semiconductor technologies finally allowed the design of reliable electronics operating at millimeter-wave frequencies. On top, advanced Fully Depleted Silicon On Insulator (FD-SOI) Complementary Metal Oxide Semiconductor (CMOS) and Silicon Germanium (SiGe) Bipolar CMOS (BiCMOS) processes enabled to co-integrate large digital blocks with frontends operating at tens or hundreds of GHz. The current under-deployment fifth-generation mobile-communication standard (5G) takes advantage of these advancements, massively exploiting the frequency bands from 24 GHz to 100 GHz. Furthermore, besides enlarging the channel bandwidth, improvements of the signal-to-noise power ratio (SNR) at the receiver input, combined with Multiple-Input Multiple-Output (MIMO) techniques provide an additional boost to the communication data-rate. Both approaches require arrays of antennas, plus electronic beam-steering which becomes essential in the case of moving transmitting-receiving pairs. Finally, social, economic, historical, and technological trends indicate that future wireless standards will require data-rates, latencies, and density of served users per square kilometer well beyond those offered by the 5G. Envisioned to be deployed towards the end of this decade, the six mobile communication standard (6G) will win future challenges thanks to the very ultra-broad bands available from 100 GHz until the tens of THz. Basic research is hence needed to address the open challenges necessary to reach the goals of future wireless communication systems, such as bandwidth and frequency operation factor-10 increase or power consumption reduction against the actual state of the art. This Habilitation thesis proposes circuit theory and concepts up to feasibility study of circuit implementation and experimental characterization in the laboratory of transceiver electronics for future high-capacity communications useful for the knowledge gain necessary for the conception of future communication systems. In detail, basic scientific research to understand the operation of millimeter-wave communication circuits implemented in 22 nm FD-SOI CMOS and 130 nm SiGe BiCMOS technologies has been performed.

Interest in millimeter (mm-) wave frequencies covering the spectrum of 30-300 GHz has been steadily increasing. Advantages such as larger absolute bandwidth and smaller form-factor have made this frequency region attractive for numerous applications, including high-speed wireless communication, sensing, material science, health, automotive radar, and space exploration. Continuous development of silicon-germanium heterojunction bipolar transistor (SiGe HBT) and associated BiCMOS technology has achieved transistors with fT/fmax of 505/720 GHz and integration with 55 nm CMOS. Such accomplishment and predictions of beyond THz performance have made SiGe BiCMOS technology the most competitive candidate for addressing the aforementioned applications. Especially for mobile applications, a critical demand for future mm-wave applications will be low DC power consumption (Pdc), which requires a substantial reduction of supply voltage and current. Conventionally, reducing the supply voltage will lead to HBTs operating close to or in the saturation region, which is typically avoided in mm-wave circuits due to expectated performance degradation and often inaccurate models. However, due to only moderate speed reduction at the forward-biased base-collector voltage (VBC) up to 0.5 V and the accuracy of the compact model HICUM/L2 also in saturation, low-power mm-wave circuits with SiGe HBTs operating in saturation offer intriguing benefits, which have been explored in this thesis based on 130 nm SiGe BiCMOS technologies: • Different low-power mm-wave circuit blocks are discussed in detail, including low-noise amplifiers (LNAs), down-conversion mixers, and various frequency multipliers covering a wide frequency range from V-band (50-75 GHz) to G-band (140-220 GHz). • Aiming at realizing a better trade-off between Pdc and RF performance, a drastic decrease in supply voltage is realized with forward-biased VBC, forcing transistors of the circuits to operate in saturation. • Discussions contain the theoretical analysis of the key figure of merits (FoMs), topology and bias selection, device sizing, and performance enhancement techniques. • A 173-207 GHz low-power amplifier with 23 dB gain and 3.2 mW Pdc, and a 72-108 GHz low-power tunable amplifier with 10-23 dB gain and 4-21 mW Pdc were designed. • A 97 GHz low-power down-conversion mixer was presented with 9.6 dB conversion gain (CG) and 12 mW Pdc. • For multipliers, a 56-66 GHz low-power frequency quadrupler with -3.6 dB peak CG and 12 mW Pdc, and a 172-201 GHz low-power frequency tripler with -4 dB peak CG and 10.5 mW Pdc were realized. By cascading these two circuits, also a 176-193 GHz low-power ×12 multiplier was designed, achieving -11 dBm output power with only 26 mW Pdc. • An integrated 190 GHz low-power receiver was designed as one receiving channel of a G-band frequency extender specifically for a VNA-based measurement system. Another goal of this receiver is to explore the lowest possible Pdc while keeping its highly competitive RF performance for general applications requiring a wide LO tuning range. Apart from the low-power design method of circuit blocks, the careful analysis and distribution of the receiver FoMs are also applied for further reduction of the overall Pdc. Along this line, this receiver achieved a peak CG of 49 dB with a 14 dB tunning range, consuming only 29 mW static Pdc for the core part and 171 mW overall Pdc, including the LO chain. • All designs presented in this thesis were fabricated and characterized on-wafer. Thanks to the accurate compact model HICUM/L2, first-pass access was achieved for all circuits, and simulation results show excellent agreement with measurements. • Compared with recently published work, most of the designs in this thesis show extremely low Pdc with highly competitive key FoMs regarding gain, bandwidth, and noise figure. • The observed excellent measurement-simulation agreement enables the sensitivity analysis of each design for obtaining a deeper insight into the impact of transistor-related physical effects on critical circuit performance parameters. Such studies provide meaningful feedback for process improvement and modeling development.:Table of Contents Kurzfassung . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii 1 Introduction 1 1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 List of symbols and acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 Technology 7 2.1 Fabrication Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.1 SiGe HBT performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.2 B11HFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.3 SG13G2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1.4 SG13D7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 Commonly Used Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.1 Grounded-sidewall-shielded microstrip line . . . . . . . . . . . . . . . . . . 12 2.2.2 Zero-impedance Transmission Line . . . . . . . . . . . . . . . . . . . . . . 15 2.2.3 Balun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.3.1 Active Balun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.3.2 Passive Balun . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3 Low-power Low-noise Amplifiers 25 3.1 173-207 GHz Ultra-low-power Amplifier . . . . . . . . . . . . . . . . . . . . . . . 25 3.1.1 Topology Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1.2 Bias Dependency of the Small-signal Performance . . . . . . . . . . . . . 27 3.1.2.1 Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.1.2.2 Bias vs Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.1.2.3 Bias vs Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.1.2.4 Bias vs Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.1.3 Bias selection and Device sizing . . . . . . . . . . . . . . . . . . . . . . . . 36 3.1.3.1 Bias Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.1.3.2 Device Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.1.4 Performance Enhancement Technologies . . . . . . . . . . . . . . . . . . . 41 3.1.4.1 Gm-boosting Inductors . . . . . . . . . . . . . . . . . . . . . . . 41 3.1.4.2 Stability Enhancement . . . . . . . . . . . . . . . . . . . . . . . 43 3.1.4.3 Noise Improvement . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.1.5 Circuit Realization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.1.5.1 Layout Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.1.5.2 Inductors Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.1.5.3 Dual-band Matching Network . . . . . . . . . . . . . . . . . . . 48 3.1.5.4 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . 50 3.1.6 Results and Discussions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.1.6.1 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.1.6.2 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . 51 3.1.6.3 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.2 72-108 GHz Low-Power Tunable Amplifier . . . . . . . . . . . . . . . . . . . . . . 55 3.2.1 Configuration, Sizing, and Bias Tuning Range . . . . . . . . . . . . . . . . 55 3.2.2 Regional Matching Network . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.2.2.1 Impedance Variation . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.2.2.2 Regional Matching Network Design . . . . . . . . . . . . . . . . 60 3.2.3 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.2.4 Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.2.4.1 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.2.4.2 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4 Low-power Down-conversion Mixers 73 4.1 97 GHz Low-power Down-conversion Mixer . . . . . . . . . . . . . . . . . . . . . 74 4.1.1 Mixer Design and Implementation . . . . . . . . . . . . . . . . . . . . . . 74 4.1.1.1 Mixer Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.1.1.2 Bias Selection and Device Sizing . . . . . . . . . . . . . . . . . . 77 4.1.1.3 Mixer Implementation . . . . . . . . . . . . . . . . . . . . . . . . 79 4.1.2 Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.1.2.1 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . 80 4.1.2.2 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.2 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5 Low-power Multipliers 87 5.1 General Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.2 56-66 GHz Low-power Frequency Quadrupler . . . . . . . . . . . . . . . . . . . . 89 5.3 172-201 GHz Low-power Frequency Tripler . . . . . . . . . . . . . . . . . . . . . 93 5.4 176-193 GHz Low-power ×12 Frequency Multiplier . . . . . . . . . . . . . . . . . 96 5.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6 Low-power Receivers 101 6.1 Receiver Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.2 LO Chain (×12) Integrated 190 GHz Low-Power Receiver . . . . . . . . . . . . . 104 6.2.1 Receiver Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.2.2 Low-power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 6.2.3 Building Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.2.3.1 LNA and LO DA . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.2.3.2 Tunable Mixer and IF BA . . . . . . . . . . . . . . . . . . . . . 111 6.2.3.3 65 GHz (V-band) Quadrupler . . . . . . . . . . . . . . . . . . . 116 6.2.3.4 G-band Tripler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.2.4 Receiver Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . 123 6.2.5 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.2.6 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 7 Conclusions 133 7.1 Summaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 7.2 Outlook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Bibliography 135 List of Figures 149 List of Tables 157 A Derivation of the Gm 159 A.1 Gm of standard cascode stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 A.2 Gm of cascode stage with Lcas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 A.3 Gm of cascode stage with Lb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 B Derivation of Yin in the stability analysis 163 C Derivation of Zin and Zout 165 C.1 Zin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 C.2 Zout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 D Derivation of the cascaded oP1dB 169 E Table of element values for the designed circuits 171

The growing demand for high data rates, reliable connections, low latency, and increased user density has driven the operating frequency of modern wireless communication systems towards the millimeter-wave (mmWave) band. Large-scale antenna arrays capable of supporting simultaneous multi-beamforming are crucial for these mmWave systems. Passive beamforming networks, particularly Butler matrices (BM), offer several advantages for mmWave applications due to their low complexity, high energy efficiency, zero DC power consumption, and ability to generate multiple orthogonal beams. However, existing BM designs are often limited to low-order matrices, supporting a restricted number of radiating elements and featuring bulky cubic structures unsuitable for the microwave range. The contributions of this work include extensions in the Butler matrix order to support a massive antenna array, simplification of the Butler matrix topology to reduce the insertion loss, and layout optimization for straightforward antenna array integration. The novel multi-beam antenna systems for the one- and two-dimensional beamforming at mmWave band are designed and experimentally validated. First of all, a theoretical analysis of the Butler matrix topology is conducted to find effective solutions for matrix order extension, simplification, and loss reduction. Then, a multi-beam system consisting of a compact 8×8 one-dimension BM and an antenna array is implemented. To further extend the number of multi-beams, a 28 GHz multi-beam array system based on high-dimension 16 × 16 one-dimension BM and 1 × 16 linear antenna array is proposed. Additionally, a 28 GHz multi-beam array system fed by a planar 16 × 16 twodimensional Butler matrix is examined. Utilizing the proposed concept for the planarization of the cubic-formed two-dimensional Butler matrix, a system implemented with the multi-layer lamination in a dramatically reduced size provides 16 spatial orthogonal beams over a conical space. Furthermore, two new concepts for the planar and uni-planar 32 × 32 two-dimensional Butler matrix are developed not only for more beams but also to reduce the required signal layers.

Die Einführung des millimeter-Wellen-Bandes eröffnet neue Perspektiven für die Radio Frequency Identification (RFID) Kommunikationssysteme. Der Enwurf des Systems im 60-GHz-Band ermöglicht die Implementierung der On-Chip Antenne und darüber hinaus die Implementierung eines RFID-Tags auf einem einzigen Chip. Dennoch ist es aufgrund der gesetzlichen Beschränkung der effektiven isotropen Strahlungsleistung (EIRP) des Lesegeräts und der erhöhten Freiraum-Dielektrikumsverluste eine Herausforderung, eine zuverlässige Kommunikationsreichweite von mehreren Millimetern zu erreichen. Neue Lösungen sind für jeden Block sowohl im Lesegerät als auch im Single-Chip-Tag erforderlich. Obwohl das Lesegerät batteriebetrieben ist, ist es immer noch eine Herausforderung, die maximal zulässigen 20 dBm IERP des Lesersenders energieeffizient zu erzeugen. Darüber hinaus sollte der Empfänger einen ausreichenden Dynamikbereich haben, um das vom Tag kommende Signal zu erkennen. Auf der Tag-Seite sind die Hauptherausforderungen das Co-Design der effizienten On-Chip-Antennen-Implementierung, die hochempfindliche Gleichrichter-Implementierung und das Rückkommunikationskonzept. Diese Arbeit konzentriert sich auf die Machbarkeitsstudie des Single-Chip-RFID-Tags und die Implementierung im Millimeterwellenbereich. Es werden zwei Rückkommunikationskonzepte untersucht - Backscattering-Rückkommunikation und eine Kommunikation unter Verwendung von Ultra-Low-Power (ULP) Radios. Beide werden in einem 22 nm FDSOI Prozess auf einem Substrat mit geringem Widerstand implementiert. Beide Tags arbeiten mit einer Versorgungsspannung von 0,4 V, um die Kommunikationsreichweite zu maximieren. Die Link-Budgets sind so ausgelegt, dass sie die regulatorischen Beschränkungen einhalten. Die Auswahl des Technologieknotens wird begründet. Verschiedene Aspekte im Zusammenhang mit der Technologie werden diskutiert, wie z. B. Geräteleistung, passiver Qualitätsfaktor, Leistungsdichte der Kondensatoren. Der Backscattering RFID-Tag wird zuerst entworfen, da er eine relativ einfachere Topologie hat. Die Probleme der Gleichrichterempfindlichkeit im Rahmen des analogen Frontends, der On-Chip-Antenneneffizienz und der konjugierten Anpassung beider werden untersucht. Eine Kommunikationsreichweite von 5 mm wird angestrebt und realisiert. Um die Kommunikationsreichweite weiter zu erhöhen, wird in der zweiten Phase ein Tag mit einer aktiven Rückkommunikation implementiert. Hier wird die Gleichrichterempfindlichkeit weiter verbessert. Es wird ein 0,4V ULP Radio entworfen, das sich die Antenne mit dem Gleichrichter über einen Single-Pole- Double-Through (SPDT) Schalter teilt. Ein Abstand von 2 cm erwies sich als realisierbar, wobei die gesetzlichen Bestimmungen eingehalten und der dynamische Bereich des Leseempfängers nicht überschritten wurde. Es wird die höchste normalisierte Kommunikationsreichweite pro Leser-EIRP erreicht. Weitere Verbesserungsmöglichkeiten werden diskutiert.