This thesis presents four-quadrant CMOS current-mode multiplier architectures based on the bipolar Gilbert cell multiplier architecture. Multipliers are designed using the CMOS subthreshold region to take advantage of the subthreshold exponential I-V relationship that closely matches bipolar modeling. It is discovered that biasing to remove drift current components and to address higher order effects such as ideality factor mismatch, threshold mismatch, body effect, and short channel effects, is important to provide a linear multiplier. It is also shown that distortion caused by device size mismatch and offset input currents can be used to cancel the distortion introduced by drift currents when designing in weak and moderate inversion. This concept allows for linear multiplier designs with larger input currents which results in dramatic improvements in bandwidth over traditional weak inversion circuits. Three multiplier circuits are simulated and fabricated in an AMIS 0.35-um process. Circuits with less than 1 % nonlinear error and distortion (THD) across 100 % dynamic input range and with bandwidths greater than 100 MHz can be built. Also, low power multiplier solutions are presented that consume less than 40 nW of dynamic power.

This thesis demonstrates that the composite cascode differential stage, operating in the subthreshold region, can form the basis of a high gain (113 dB) and low-power op amp (28.1 µW). The circuit can be fabricated without adding a compensation capacitance. The advantages of this architecture include high voltage gain, low bandwidth, low harmonic distortion, low quiescent current and power, and small chip area. These advantages suggest that this design might be well-suited for biomedical applications where low power, low noise bio-signal amplifiers capable of amplifying signals in the millihertz-to-kilohertz range is required.