Digital computers have changed human society in a profound way over the last 50 years. Key properties that contribute to the success of the computer are flexible programmability and fast access to large amounts of data and instructions. Effective access to algorithms and data is a fundamental property that limits the capabilities of computer systems. For PC computers, the main memory consists of dynamic random access memory (DRAM). Communication between memory and processor has traditionally been performed over a multi-drop bus. Signal frequencies on these buses have gradually increased in order to keep up with the progress in integrated circuit data processing capabilities. Increased signal frequencies have exposed the inherent signal degradation effects of a multidrop bus structure. As of today, the main approach to tackle these effects has been to reduce the number of endpoints of the bus structure. Though improvements in DRAM memory technology have increased the available memory size at each endpoint, the increase has not been able to fully fulfill the demand for larger system memory capacity. Different bus structural changes have been used to overcome this problem. All are different compromises between access latency, data transmission capacity, memory capacity, and implementation costs. In this thesis we focus on using the signal processing capabilities of a modern integrated circuit technology as an alternative to bus structural changes. This has the potential to give low latency, high memory capacity, and relatively high data transmission capacity at an additional cost limited to integrated circuit blocks. We first use information theory to estimate the unexplored potential of existing multi-drop bus structures. Hereby showing that reduction of the number of endpoints for multi-drop buses, is by no means based on the fundamental limit of the data transmission capacity of the bus structure. Two test-chips have been designed and fabricated to experimentally demonstrate the feasibility of several Gb/s data-rates over multidrop buses, with limited cost overhead and no latency penalty. The test-chips implement decision feedback equalization, adopted for high speed multi-drop use. The equalizers feature digital filter implementations which, in combination with high speed DACs, enable the use of long digital filters for high speed decision feedback equalization. Blind adaptation has also been implemented to demonstrate extraction of channel characteristics during data transmission. The use of single sided equalization has been proposed in order to limit the need for equalization implementation to the host side of a DRAM memory bus. Furthermore, we propose to utilize the reciprocal properties of the communication channel to ensure that single sided equalization can be performed without any channel characterization hardware on the memory chips. Finally, issues related to evaluation of high-speed channels are addressed and the on-chip structures used for channel evaluation in this project are presented.