As integrated circuits (ICs) are scaled down to deep submicron regime, interconnect delay becomes increasingly dominant over intrinsic gate delay. To solve the issue, two realistic methods are accepted popularly. On the one hand we use copper as the conductor for multilevel interconnects to decrease the resistance part of the RC delay. On the other hand we should reduce the coupling capacitance between the metal lines and this requires a low dielectric constant material. However, some difficulties come up in integrating low-k material with copper wires, including dielectric integrity and high diffusivity of copper ions. In order to prevent copper from penetrating into dielectric material under high electric fields and operation temperature, barrier dielectric have been developed to enhance resistance against copper drift. Silicon carbide (SixCy) with lower dielectric constant (k=4~5) is a promising barrier dielectric material to replace typically used silicon nitride (SixNy), (k~8). In this thesis, we will discuss the basic material properties of silicon carbide and the issues which will meet in process integration and actual working such as thermal cycles and operating under an electric field and a high temperature environment simultaneously. We investigated the conduction mechanism of the leakage current and tried to extract the physical parameters among it. In addition, the electrical properties of Silicon carbide at low temperature were also an important part of our research. Finally, we proposed some reasonable models to demonstrate the phenomenon and results we observed.

L’évolution tendant à réduire la taille et augmenter la complexité des circuits électroniques modernes, est en train de ralentir du fait des limitations technologiques, qui génèrent beaucoup de d’imperfections et de defaults durant la fabrication ou la durée de vie de la puce. Les FPGAs sont utilisés dans les systèmes numériques complexes, essentiellement parce qu’ils sont reconfigurables et rapide à commercialiser. Pour garder une grande fiabilité de tels systèmes, les FPGAs doivent être testés minutieusement pour les defaults. L’optimisation de l’architecture des FPGAs pour l’économie de surface et une meilleure routabilité est un processus continue qui impacte directement la testabilité globale et de ce fait, la fiabilité. Cette thèse présente une stratégie complète pour le test et le diagnostique des defaults de fabrication des “mesh-based FPGA” contenant une nouvelle topologie d’interconnections à plusieurs niveaux, ce qui promet d’apporter une meilleure routabilité. Efficacité des schémas proposes est analysée en termes de temps de test, couverture de faute et résolution de diagnostique. / The evolution trend of shrinking feature size and increasing complexity in modern electronics is being slowed down due to physical limits that generate numerous imperfections and defects during fabrication steps or projected life time of the chip. Field Programmable Gate Arrays (FPGAs) are used in complex digital systems mainly due to their reconfigurability and shorter time-to-market. To maintain a high reliability of such systems, FPGAs should be tested thoroughly for defects. FPGA architecture optimization for area saving and better signal routability is an ongoing process which directly impacts the overall FPGA testability, hence the reliability. This thesis presents a complete strategy for test and diagnosis of manufacturing defects in mesh-based FPGAs containing a novel multilevel interconnects topology which promises to provide better area and routability. Efficiency of the proposed test schemes is analyzed in terms of test cost, respective fault coverage and diagnostic resolution.