In many multimedia applications, a little error in the output results is allowable. Therefore, this thesis presents an iterative floating-point multiplier with multiple precision to reduce the energy consumption of floating-point multiplication operations. The multiplier can provide the users with three kinds of modes. The distinction among the three modes is the accepted output error and the achievable energy saving through reducing the length of mantissa in the multiplication operation. In addition, to reduce the area of multiple precision floating-point multiplier we use the iterative structure to implement the mantissa multiplier in a floating point multiplier. Moreover the C++ language is adopted to evaluate the product error between each mode and the IEEE754 single precision multiplier. When the multimedia applications request high precision, the multiple precision floating-point multiplier will iteratively execute the 4-2 compression tree three times and the product error is around 10e-5%. The second-mode with the middle accuracy will iteratively execute the 4-2 compression tree two times and the product error is around 10e-3%. The third mode with the lowest accuracy will execute the 4-2 compression tree once and the product error is around 1%, it requires less execution cycle number. When compared with the tree-stage IEEE754 single-precision multiplier, the proposed iterative floating-point multiplier can save 42.54% area. For IDCT application, it can save 37.78% energy under 1% error constraint, For YUV to RGB application, it can save 31.36% energy under 1.1% error constraint. The experimental results demonstrate that the proposed multiple precision iterative floating-point multiplier can significantly reduce the energy consumption of multimedia applications that allow a little output distortion

Testing is necessary factor to guarantee that ICs operate according to specifications before being delivered to customers. Testing is a process used to identify ICs containing imperfections or manufacturing defects that may cause failures. Inaccuracy and imperfections can be introduced during the fabrication of the chips due to the complex mechanical and chemical steps required during the manufacturing processes. The testing process step applies test patterns to circuits and analyzes their responses. This work focuses on VLSI circuit testing with two implementations for DFT (Design for testability); the first is an ATPG tool for sequential circuits and the second is a BIT (Built in Test) circuit for high frequency signal classification.There has been a massive increase in the number of transistors integrated in a chip, and the complexity of the circuit is increasing along with it. This growth has become a bottleneck for the test developers. The proposed ATPG tool was designed for testing sequential circuits. Scan Chains in Design For Testability (DFT) gained more prominence due to the increase in the complexity of the modern circuits. As the test time increases along with the number of memory elements in the circuit, new and improved methods are needed. Even though scan chains implementation effectively increases observability and controllability, a big portion of the time is wasted while shifting in and shifting out the test patterns through the scan chain. Additionally, the modern applications require operating speed at higher frequencies and there is a growing demand in testing equipment capable to test CMOS circuits utilized in high frequency applications.With the modern applications requiring operating speed at higher frequencies, there is a growing demand in testing equipment capable to test CMOS circuits utilized in high frequency applications. Two main problems have been associated when using external test equipment to test high frequency circuits; the effect of the resistance and capacitance of the probe on the performance of the circuit under test which leads to a faulty evaluation; and the cost of a dedicated high frequency tester. To solve these problems innovative test techniques are needed such as Built In Test (BIT) where self-evaluation takes place with a small area overhead and reduced requirements for external equipment. In the proposed methodology a Built In Test (BIT) detection circuit provides an efficient way to transform the high frequency response of the circuit under test into a DC signal.This work is focused in two major fields. The first topic is on VLSI circuit testing with two implementations for DFT (Design for testability); the first is an ATPG tool for sequential circuits and the second is a BIT (Built in Test) circuit for high frequency signal classification as explained. The second topic is focused on efficient implementations of arithmetic operations in arbitrary long numbers with emphasis to addition. Arbitrary-Precision arithmetic refers to a set of data structures and algorithms which allows to process much greater numbers that exceed the standard data types. . An application example where arbitrary long numbers are widely used is cryptography, because longer numbers offer higher encryption security. Modern systems typically employ up to 64-bit registers, way less than what an arbitrary number requires, while conventional algorithms do not exploit hardware characteristics as well. Mathematical models such as weather prediction and experimental mathematics require high precision calculations that exceed the precision found in most Arithmetic Logic Units (ALU). In this work, we propose a new scalable algorithm to add arbitrary long numbers. The algorithm performs bitwise logic operations rather than arithmetic on 64-bit registers. We propose two approaches of the same algorithm that utilize the same basic function created according to the rules of binary addition

In some antenna applications, having high directivity while keeping the antenna dimensions small is desired, which can be obtained by use of superdirective arrays. Superdirective arrays have been popular in academic world since a superdirective array provides higher directivity than the uniformly excited antenna array of same length. In this thesis, superdirective arrays are investigated by making high precision numerical computations. Superdirective array element excitations, array factors and directivities are inspected for different number of elements. Superdirective array pattern and directivity features are compared to uniformly excited array pattern and directivities. Superdirective array tolerance is investigated by examination of array element excitation sensitivities. Bandwidth of superdirective arrays is also inspected. Multiple Precision Toolbox is used during numerical computations in Matlab.