Silicon-based nanostructures are essential building blocks for nanoelectronic devices and nano-electromechanical systems (NEMS). As the silicon device size continues to scale down, the surface to volume ratio becomes larger, rendering the properties of surfaces and interfaces more important for improving the properties of the nano-devices and systems. One of those properties is the friction, which is important in controlling the functionality and reliability of the nano-device and systems. The goal of this dissertation is to investigate the deformation and friction behaviors of single crystalline silicon nanolines (SiNLs) using nanoindentation techniques. Following an introduction and a summary of the theoretical background of contact friction in Chapters 1 and 2, the results of this thesis are presented in three chapters. In Chapter 3, the fabrication of the silicon nanolines is described. The fabrication method yielded high-quality single-crystals with line width ranging from 30nm to 90nm and height to width aspect ratio ranging from 10 to 25. These SiNL structures have properties and dimensions well suited for the study of the mechanical and friction behaviors at the nanoscale. In Chapter 4, we describe the study of the mechanical properties of SiNLs using the nanoindentation method. The loading-displacement curves show that the critical load to induce the buckling of the SiNLs can be correlated to the contact friction and geometry of SiNLs. A map was built as a guideline to describe the selection of buckling modes. The map was divided into three regions where different regions correlate to different buckling modes including Mode I, Mode II and slidingbending of SiNLs. In Chapter 5, we describe the study of the contact friction of the SiNL structures. The friction coefficient at the contact was extracted from the loaddisplacement curves. Subsequently, the frictional shear stress was evaluated. In addition, the effect of the interface between the indenter and SiNLs was investigated using SiNLs with surfaces coated by a thin silicon dioxide or chromium film. The material of the interface was found to influence significantly the contact friction and its behavior. Cyclic loading-unloading experiments showed the friction coefficient dramatically changed after only a few loading cycles, indicating the contact history is important in controlling the friction behaviors of SiNLs at nanoscales. This thesis is concluded with a summary of the results and proposed future studies. / text

Esta Tese apresenta os resultados da simulação do transporte eletrônico em três dimensões (3D) no nano dispositivo eletrônico conhecido como “SOI-FinFET”. Este dispositivo é um transistor MOS em tecnologia Silício sobre Isolante – “Silicon-on- Insulator”, SOI – com porta dupla e cujo canal e zonas de fonte e dreno são realizadas em uma estrutura nanométrica vertical de silício chamada de “finger” ou “fin”. Como introdução ao dispositivo em questão, é feita uma revisão básica sobre a tecnologia e transistores SOI e sobre MOSFETs de múltiplas portas. A implementação de um modelo tipo “charge-sheet” para o transistor SOI-MOSFET totalmente depletado e uma modelagem deste dispositivo em altas frequências também é apresentada. A geometria do “fin” é escalada para valores menores do que 100 nm, com uma espessura entre 10 e 20 nm. Um dos objetivos deste trabalho é a definição de parâmetros para o SOI-FinFET que o viabilizem para a tecnologia de 22 nm, com um comprimento efetivo de canal menor do que 20 nm. O transistor FinFET e uma estrutura básica simplificada para simulação numérica em 3D são descritos, sendo utilizados dados de tecnologias atuais de fabricação. São apresentados resultados de simulação numérica 3D (curvas ID-VG, ID-VD, etc.) evidenciando as principais características de funcionamento do FinFET. É analisada a influência da espessura e dopagem do “fin” e do comprimento físico do canal em parâmetros importantes como a tensão de limiar e a inclinação de sublimiar. São consideradas e analisadas duas possibilidades de dopagens da área ativa do “fin”: (1) o caso em que esta pode ser considerada não dopada, sendo baixíssima a probabilidade da presença de dopantes ativos, e (2) o caso de um alto número de dopantes ativos (> 10 é provável). Uma comparação entre dois simuladores numéricos 3D de dispositivos é realizada no intuito de explicitar diferenças entre modelos de simulação e características de descrição de estruturas 3D. São apresentadas e analisadas medidas em dispositivos FinFET experimentais. Dois métodos de extração de resistência série parasita são utilizados em FinFETs simulados e caracterizados experimentalmente. Para finalizar, são resumidas as principais conclusões deste trabalho e são propostos os trabalhos futuros e novas diretivas na pesquisa dos transistores FinFETs. / This thesis presents the results of 3D-numerical simulation of electron transport in double-gate SOI-FinFETs in the decanometer size range. A basic review on the SOI technology and multiple gates MOSFETs is presented. The implementation of a chargesheet model for the fully-depleted SOI-MOSFET and a high frequency modeling of this device are first presented for a planar device topology. The second part of this work deals with FinFETs, a non-planar topology. The geometry of the silicon nano-wire (or “fin”) in this thesis is scaled down well below 100 nm, with fin thickness in the range of 10 to 20 nm. This work addresses the parameters for a viable 22 nm CMOS node, with electrical effective channel lengths below 20 nm. The basic 3D structure of the FinFET transistor is described in detail, then it is simulated with various device structural parameters, and results of 3D-numerical simulation (ID-VG curves, ID-VD, etc.), showing the main features of operation of this device, are presented. The impacts of varying silicon fin thicknesses, physical channel lengths, and silicon fin doping concentration on both the average threshold voltage and the subthreshold slope are investigated. With respect to the doping concentration, the discrete and highly statistical nature of impurity presence in the active area of the nanometer-range fin is considered in two limiting cases: (1) the zero-doping or undoped case, for highly improbable presence of active dopants, and (2) the many-dopants case, or high number (> 10 are probable) of active dopants in the device channel. A comparison between two 3D-numerical device simulators is performed in order to clarify differences between simulation models and features of the description of 3D structures. A structure for SOIFinFETs is optimized, for the undoped fin, showing its applicability for devices with electrical effective channel lengths below 20 nm. SOI-FinFET measurements were performed on experimental devices, analyzed and compared to device simulation results. This thesis uses parasitic resistance extraction methods that are tested in FinFET simulations and measurements. Finally, the main conclusions of this work are summarized and the future work and new directions in the FinFETs research are proposed.

Esta Tese apresenta os resultados da simulação do transporte eletrônico em três dimensões (3D) no nano dispositivo eletrônico conhecido como “SOI-FinFET”. Este dispositivo é um transistor MOS em tecnologia Silício sobre Isolante – “Silicon-on- Insulator”, SOI – com porta dupla e cujo canal e zonas de fonte e dreno são realizadas em uma estrutura nanométrica vertical de silício chamada de “finger” ou “fin”. Como introdução ao dispositivo em questão, é feita uma revisão básica sobre a tecnologia e transistores SOI e sobre MOSFETs de múltiplas portas. A implementação de um modelo tipo “charge-sheet” para o transistor SOI-MOSFET totalmente depletado e uma modelagem deste dispositivo em altas frequências também é apresentada. A geometria do “fin” é escalada para valores menores do que 100 nm, com uma espessura entre 10 e 20 nm. Um dos objetivos deste trabalho é a definição de parâmetros para o SOI-FinFET que o viabilizem para a tecnologia de 22 nm, com um comprimento efetivo de canal menor do que 20 nm. O transistor FinFET e uma estrutura básica simplificada para simulação numérica em 3D são descritos, sendo utilizados dados de tecnologias atuais de fabricação. São apresentados resultados de simulação numérica 3D (curvas ID-VG, ID-VD, etc.) evidenciando as principais características de funcionamento do FinFET. É analisada a influência da espessura e dopagem do “fin” e do comprimento físico do canal em parâmetros importantes como a tensão de limiar e a inclinação de sublimiar. São consideradas e analisadas duas possibilidades de dopagens da área ativa do “fin”: (1) o caso em que esta pode ser considerada não dopada, sendo baixíssima a probabilidade da presença de dopantes ativos, e (2) o caso de um alto número de dopantes ativos (> 10 é provável). Uma comparação entre dois simuladores numéricos 3D de dispositivos é realizada no intuito de explicitar diferenças entre modelos de simulação e características de descrição de estruturas 3D. São apresentadas e analisadas medidas em dispositivos FinFET experimentais. Dois métodos de extração de resistência série parasita são utilizados em FinFETs simulados e caracterizados experimentalmente. Para finalizar, são resumidas as principais conclusões deste trabalho e são propostos os trabalhos futuros e novas diretivas na pesquisa dos transistores FinFETs. / This thesis presents the results of 3D-numerical simulation of electron transport in double-gate SOI-FinFETs in the decanometer size range. A basic review on the SOI technology and multiple gates MOSFETs is presented. The implementation of a chargesheet model for the fully-depleted SOI-MOSFET and a high frequency modeling of this device are first presented for a planar device topology. The second part of this work deals with FinFETs, a non-planar topology. The geometry of the silicon nano-wire (or “fin”) in this thesis is scaled down well below 100 nm, with fin thickness in the range of 10 to 20 nm. This work addresses the parameters for a viable 22 nm CMOS node, with electrical effective channel lengths below 20 nm. The basic 3D structure of the FinFET transistor is described in detail, then it is simulated with various device structural parameters, and results of 3D-numerical simulation (ID-VG curves, ID-VD, etc.), showing the main features of operation of this device, are presented. The impacts of varying silicon fin thicknesses, physical channel lengths, and silicon fin doping concentration on both the average threshold voltage and the subthreshold slope are investigated. With respect to the doping concentration, the discrete and highly statistical nature of impurity presence in the active area of the nanometer-range fin is considered in two limiting cases: (1) the zero-doping or undoped case, for highly improbable presence of active dopants, and (2) the many-dopants case, or high number (> 10 are probable) of active dopants in the device channel. A comparison between two 3D-numerical device simulators is performed in order to clarify differences between simulation models and features of the description of 3D structures. A structure for SOIFinFETs is optimized, for the undoped fin, showing its applicability for devices with electrical effective channel lengths below 20 nm. SOI-FinFET measurements were performed on experimental devices, analyzed and compared to device simulation results. This thesis uses parasitic resistance extraction methods that are tested in FinFET simulations and measurements. Finally, the main conclusions of this work are summarized and the future work and new directions in the FinFETs research are proposed.

Esta Tese apresenta os resultados da simulação do transporte eletrônico em três dimensões (3D) no nano dispositivo eletrônico conhecido como “SOI-FinFET”. Este dispositivo é um transistor MOS em tecnologia Silício sobre Isolante – “Silicon-on- Insulator”, SOI – com porta dupla e cujo canal e zonas de fonte e dreno são realizadas em uma estrutura nanométrica vertical de silício chamada de “finger” ou “fin”. Como introdução ao dispositivo em questão, é feita uma revisão básica sobre a tecnologia e transistores SOI e sobre MOSFETs de múltiplas portas. A implementação de um modelo tipo “charge-sheet” para o transistor SOI-MOSFET totalmente depletado e uma modelagem deste dispositivo em altas frequências também é apresentada. A geometria do “fin” é escalada para valores menores do que 100 nm, com uma espessura entre 10 e 20 nm. Um dos objetivos deste trabalho é a definição de parâmetros para o SOI-FinFET que o viabilizem para a tecnologia de 22 nm, com um comprimento efetivo de canal menor do que 20 nm. O transistor FinFET e uma estrutura básica simplificada para simulação numérica em 3D são descritos, sendo utilizados dados de tecnologias atuais de fabricação. São apresentados resultados de simulação numérica 3D (curvas ID-VG, ID-VD, etc.) evidenciando as principais características de funcionamento do FinFET. É analisada a influência da espessura e dopagem do “fin” e do comprimento físico do canal em parâmetros importantes como a tensão de limiar e a inclinação de sublimiar. São consideradas e analisadas duas possibilidades de dopagens da área ativa do “fin”: (1) o caso em que esta pode ser considerada não dopada, sendo baixíssima a probabilidade da presença de dopantes ativos, e (2) o caso de um alto número de dopantes ativos (> 10 é provável). Uma comparação entre dois simuladores numéricos 3D de dispositivos é realizada no intuito de explicitar diferenças entre modelos de simulação e características de descrição de estruturas 3D. São apresentadas e analisadas medidas em dispositivos FinFET experimentais. Dois métodos de extração de resistência série parasita são utilizados em FinFETs simulados e caracterizados experimentalmente. Para finalizar, são resumidas as principais conclusões deste trabalho e são propostos os trabalhos futuros e novas diretivas na pesquisa dos transistores FinFETs. / This thesis presents the results of 3D-numerical simulation of electron transport in double-gate SOI-FinFETs in the decanometer size range. A basic review on the SOI technology and multiple gates MOSFETs is presented. The implementation of a chargesheet model for the fully-depleted SOI-MOSFET and a high frequency modeling of this device are first presented for a planar device topology. The second part of this work deals with FinFETs, a non-planar topology. The geometry of the silicon nano-wire (or “fin”) in this thesis is scaled down well below 100 nm, with fin thickness in the range of 10 to 20 nm. This work addresses the parameters for a viable 22 nm CMOS node, with electrical effective channel lengths below 20 nm. The basic 3D structure of the FinFET transistor is described in detail, then it is simulated with various device structural parameters, and results of 3D-numerical simulation (ID-VG curves, ID-VD, etc.), showing the main features of operation of this device, are presented. The impacts of varying silicon fin thicknesses, physical channel lengths, and silicon fin doping concentration on both the average threshold voltage and the subthreshold slope are investigated. With respect to the doping concentration, the discrete and highly statistical nature of impurity presence in the active area of the nanometer-range fin is considered in two limiting cases: (1) the zero-doping or undoped case, for highly improbable presence of active dopants, and (2) the many-dopants case, or high number (> 10 are probable) of active dopants in the device channel. A comparison between two 3D-numerical device simulators is performed in order to clarify differences between simulation models and features of the description of 3D structures. A structure for SOIFinFETs is optimized, for the undoped fin, showing its applicability for devices with electrical effective channel lengths below 20 nm. SOI-FinFET measurements were performed on experimental devices, analyzed and compared to device simulation results. This thesis uses parasitic resistance extraction methods that are tested in FinFET simulations and measurements. Finally, the main conclusions of this work are summarized and the future work and new directions in the FinFETs research are proposed.

<p>This dissertation hypothesizes,</p><p><italic>"It is possible to design a self-assembled, nanoscale, high-speed, resonance energy transfer device exhibiting non-linear gain with a few molecules."</italic></p><p>The report recognizes DNA self-assembly, a relatively inexpensive and a massively parallel fabrication process, as a strong candidate for self-assembled RET systems. It successfully investigates into the design and simulations of a novel sequential self-assembly process employed to realize the goal of creating large, scalable, fully-addressable DNA nanostructure-substrate for future molecular circuitry. </p><p>As a pre-cursor to the final device modeling various RET wire designs for interconnecting nanocircuits are presented and their modeling and simulation results are discussed. A chromophore RET system using a biomolecular sensor as a proof-of-concept argument that shows it is possible to model and characterize chromophore systems as a first step towards device modeling is also discussed. </p><p>Finally, the thesis report describes in detail the design, modeling, characterization, and fabrication of the Closed-Diffusive Exciton Valve: a self-assembled, nanoscale (area of 17.34 nm<super>2</super>), high-speed (3.5 ps to 6 ps) resonance energy transfer device exhibiting non-linear gain using only 10 molecules, thus confirming the hypothesis. It also recognized improvements that can be made in the future to facilitate better device operation and suggested various applications.</p> / Dissertation

Selon la feuille de route des industriels de la microélectronique (ITRS), la dimension critiqueminimum des MOSFET en 2026 ne devrait être que de 6 nm [1]. La miniaturisation du CMOS reposeessentiellement sur deux approches, à savoir la réduction des dimensions géométriques physiques etdes dimensions équivalentes. La réduction géométrique des dimensions conduit à la diminution desdimensions critiques selon la « loi » de Moore, qui définit les tendances de l’industrie dessemiconducteurs. Comme la taille des dispositifs est réduite de façon importante, davantage d’effortssont consentis pour maintenir les performances des composants en dépit des effets de canaux courts,des fluctuations induites par le nombre de dopants…. [2-4]. D’autre part, la réduction des dimensionséquivalentes devient de plus en plus importante de nos jours et de nouvelles solutions pour laminiaturisation reposant sur la conception et les procédés technologiques sont nécessaires. Pour cela,des solutions nouvelles sont nécessaires, en termes de matériaux, d’architectures de composants et detechnologies, afin d’atteindre les critères requis pour la faible consommation et les nouvellesfonctionnalités pour les composants futurs (“More than Moore” et “Beyond CMOS”). A titred’exemple, les transistors à film mince (TFT) sont des dispositifs prometteurs pour les circuitsélectroniques flexibles et transparents. / Novel advanced metal-oxide semiconductor (MOS) devices such as fully-depleted-silicon-on-insulator (FD-SOI) Tri-gate transistor, junctionless transistor, and amorphous-oxide-semiconductor thin film transistor were developed for continuing down-scaling trend and extending the functionality of CMOS technology, for example, the transparency and the flexibility. In this dissertation, the electrical characteristics and modeling of these advanced MOS devices are presented and they are analyzed. The sidewall mobility trends with temperature in multi-channel tri-gate MOSFET showed that the sidewall conduction is dominantly governed by surface roughness scattering. The degree of surface roughness scattering was evaluated with modified mobility degradation factor. With these extracted parameters, it was noted that the effect of surface roughness scattering can be higher in inversion-mode nanowire-like transistor than that of FinFET. The series resistance of multi-channel tri-gate MOSFET was also compared to planar device having same channel length and channel width of multi-channel device. The higher series resistance was observed in multi-channel tri-gate MOSFET. It was identified, through low temperature measurement and 2-D numerical simulation, that it could be attributed to the variation of doping concentration in the source/drain extension region in the device. The impact of channel width on back biasing effect in n-type tri-gate MOSFET on SOI material was also investigated. The suppressed back bias effects was shown in narrow device (Wtop_eff = 20 nm) due to higher control of front gate on overall channel, compared to the planar device (Wtop_eff = 170 nm). The variation of effective mobility in both devices was analyzed with different channel interface of the front channel and the back channel. In addition, 2-D numerical simulation of the the gate-to-channel capacitance and the effective mobility successfully reconstructed the experimental observation. The model for the effective mobility was inherited from two kinds of mobility degradations, i.e. different mobility attenuation along lateral and vertical directions of channel and additional mobility degradation in narrow device due to the effect of sidewall mobility. With comparison to inversion-mode (IM) transistors, the back bias effect on tri-gate junctionless transistors (JLTs) also has been investigated using experimental results and 2-D numerical simulations. Owing to the different conduction mechanisms, the planar JLT shows more sensitive variation on the performance by back biasing than that of planar IM transistors. However, the back biasing effect is significantly suppressed in nanowire-like JLTs, like in extremely narrow IM transistors, due to the small portion of bulk neutral channel and strong sidewall gate controls. Finally, the characterization method was comprehensively applied to a-InHfZnO (IHZO) thin film transistor (TFT). The series resistance and the variation of channel length were extracted from the transfer curve. And mobility values extracted with different methods such as split C-V method and modified Y-function were compared. The static characteristic evaluated as a function of temperature shows the degenerate behavior of a-IHZO TFT inversion layer. Using subthreshold slope and noise characteristics, the trap information in a-IHZO TFT was also obtained. Based on experimental results, a numerical model for a-IHZO TFT was proposed, including band-tail states conduction and interface traps. The simulated electrical characteristics were well-consistent to the experimental observations. For the practical applications of novel devices, the electrical characterization and proper modeling are essential. These attempts shown in the dissertation will provides physical understanding for conduction of these novel devices.

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