Enormous demands for fast and low-power computing and memory building blocks for consumer electronics, such as smartphones or tablets, have led to the emergence of silicon nanowire transistors a decade ago. Along with the Si-based nanotechnology, the silicon compatible optical and chemical sensing applications have boosted the research on hybrid devices that combine the organic and inorganic materials. Apart from the revolution in the device dimensions, the rapid growth of artificial intelligence in the software industry brunch requires the next generation’s computers with the revolutionized hybrid device architecture. Implementing such new devices can effectively perform machine learning tasks without the massive consumption of energy. The hybrid Si nanowire devices have an excellent capability to replace the conventional computing element by providing new functionalities of combined materials to the traditional transistor devices preserving the advantage of CMOS technology. A goal of this thesis is to develop functional hybrid Si nanowire-based transistors modulated by the stimuli-dependent gate to go beyond the current digital building blocks. The hybrid devices converge semiconductor channel and various materials from organic molecules to silicate composite as a gate of the transistor. External stimuli change the electronic state of the gate materials which is transformed to the gate potential of the transistors. First, this thesis studies the electronic characteristics of the Si nanowire FETs under the optical stimulus. Optical stimulus induces the strong conductance change on bare Si nanowire FETs. Under the light with low power intensity, the transistor shows an unconventional negative photoconductance (NPC) which is dependent on the doping concentration of the nanowire and the wavelength of the incident light. The dopants ions and surface states cause photo-generated hot electrons trapping which restricts conventional photoconductance in the semiconductor. In the hybrid device, however, the gate material on the Si dioxide layer plays a significant role in the optoelectronic modulation of the FET device. This thesis demonstrates that an organic photochromic material, porphyrin, wrapping around the nanowire channel acts as an optical gate of the Si nanowire transistor. The diffusive property of electrons in the molecular film decides the optical switching dynamics and efficiency. Further, this thesis introduces new functional gate material, sol-gel derived ion-doped silicate film, based on the availability of stimulus-dependent gate modulation. This amorphous and transparent silicate film shows memristive property due to the ionic redistribution in the film under bias condition. Interestingly, the sol-gel film-coated Si nanowire FETs the devices show a double gate effect cooperating with a back gate under light illumination which is due to the channel separation in the fin structure of the nanowire. In addition, the sol-gel silicate film-coated Si nanowire transistor emulates the neuronal plasticity with pulsed gate stimulation, namely “neurotransistor.” Because of the mobile ions in the silicate film, the transistor has a short-term memory and mimics membrane potential change of the neuron cell. The neurotransistor could be used as a computing node in the physical neural network for hardware machine learning. This work demonstrates that the physical properties of the gate material decide the transfer characteristics and time-dependent dynamics of the hybrid Si nanowire transistors. The optical and neuromorphic gate features of the hybrid transistors would accelerate the advancement of an optical or brain-like computing machine.

Electrostatic Discharge (ESD) is a significant hazard to electronic components and systems. Based on a specific processing technology, a given circuit application requires a customized ESD consideration that includes the devices’ operating voltage, leakage current, breakdown constraints, and footprint. As new technology nodes mature every 3-5 years, design of effective ESD protection solutions has become more and more challenging due to the narrowed design window, elevated electric field and current density, as well as new failure mechanisms that are not well understood. The endeavor of this research is to develop novel, effective and robust ESD protection solutions for both emerging technologies and modern complementary metal–oxide–semiconductor (CMOS) technologies. The Si nanowire field-effect transistors are projected by the International Technology Roadmap for Semiconductors as promising next-generation CMOS devices due to their superior DC and RF performances, as well as ease of fabrication in existing Silicon processing. Aiming at proposing ESD protection solutions for nanowire based circuits, the dimension parameters, fabrication process, and layout dependency of such devices under Human Body Mode (HBM) ESD stresses are studied experimentally in company with failure analysis revealing the failure mechanism induced by ESD. The findings, including design methodologies, failure mechanism, and technology comparisons should provide practical knowhow of the development of ESD protection schemes for the nanowire based integrated circuits. Organic thin-film transistors (OTFTs) are the basic elements for the emerging flexible, printable, large-area, and low-cost organic electronic circuits. Although there are plentiful studies focusing on the DC stress induced reliability degradation, the operation mechanism of OTFTs iv subject to ESD is not yet available in the literature and are urgently needed before the organic technology can be pushed into consumer market. In this work, the ESD operation mechanism of OTFT depending on gate biasing condition and dimension parameters are investigated by extensive characterization and thorough evaluation. The device degradation evolution and failure mechanism under ESD are also investigated by specially designed experiments. In addition to the exploration of ESD protection solutions in emerging technologies, efforts have also been placed in the design and analysis of a major ESD protection device, diodetriggered-silicon-controlled-rectifier (DTSCR), in modern CMOS technology (90nm bulk). On the one hand, a new type DTSCR having bi-directional conduction capability, optimized design window, high HBM robustness and low parasitic capacitance are developed utilizing the combination of a bi-directional silicon-controlled-rectifier and bi-directional diode strings. On the other hand, the HBM and Charged Device Mode (CDM) ESD robustness of DTSCRs using four typical layout topologies are compared and analyzed in terms of trigger voltage, holding voltage, failure current density, turn-on time, and overshoot voltage. The advantages and drawbacks of each layout are summarized and those offering the best overall performance are suggested at the end