Submitted by PPG Ci?ncia da Computa??o (ppgcc@pucrs.br) on 2018-07-06T13:04:33Z No. of bitstreams: 1 WILLIAM SCHNEIDER_DIS.pdf: 3430246 bytes, checksum: 5fc61ba11d1155b509058a5d6a0c34b9 (MD5) / Approved for entry into archive by Sheila Dias (sheila.dias@pucrs.br) on 2018-07-10T14:27:37Z (GMT) No. of bitstreams: 1 WILLIAM SCHNEIDER_DIS.pdf: 3430246 bytes, checksum: 5fc61ba11d1155b509058a5d6a0c34b9 (MD5) / Made available in DSpace on 2018-07-10T14:37:58Z (GMT). No. of bitstreams: 1 WILLIAM SCHNEIDER_DIS.pdf: 3430246 bytes, checksum: 5fc61ba11d1155b509058a5d6a0c34b9 (MD5) Previous issue date: 2014-03-13 / The increase in the number of cores available in Systems on a Chip has enabled the design of circuits with increasingly aggressive specifications. Efficient interconnection architectures such as intrachip networks are critical to the viability of these projects. However, measuring and comparing performanceof these networks for a given system is still a challenging task, which results from: (i) the complexity imposed by the abundance of available options in the design space of these networks; (ii) the current non-adoption of a unique evaluation platform to compare different networks proposals; (iii) the fact that the network traffic has a greater influence on the performance of such networks than any other design characteristic. This work has as main strategic goal the evaluation and comparison of different intrachip network architectures through the use of a unified evaluation platform. It adopts Nocbench, a recent platform, already validated in some contexts and proposed as a standard for the evaluation of intrachip networks. The employed evaluation method is based on the simulation of networks and uses as input traffic and computation models described in the form of traces, both extracted from real application. The main contributions of this work reside in: (i) the proposal of several enhancements to the chosen platform; (ii) the development of modules added to integrate the networks Hermes HS,Hermes OO, Hermes TB, Hermes VC, and YeaH from the author?s research group to the platform; (iii) the enhancement of the platform performance evaluation process, through the inclusion of metrics usually employed to compare intrachip networks, including: latency, throughput and jitter. A set of experiments validates the contributions and demonstrate the use the Nocbench platform as a useful tool in the comparison of intrachip networks of diverse origins. / O aumento no n?mero de n?cleos presentes em Sistemas Integrados em Chip tem proporcionado o projeto de circuitos com especifica??es cada vez mais agressivas. Arquiteturas de interconex?o eficientes tais como as redes intrachip s?o fundamentais para a viabilidade destes projetos. Entretanto, medir e comparar o desempenho destas redesainda ? uma tarefa desafiadora, resultado: (i) da complexidade imposta pela abund?ncia de op??es dispon?veis no espa?o de projeto destas redes; (ii) da atual n?o ado??o de uma mesma plataforma de avalia??o para a compara??o de diferentes propostas de redes; (iii) e do fato de o tr?fego de rede exercer uma influ?ncia muito maior do que qualquer caracter?stica de projeto no desempenho destas. Este trabalho tem como principal objetivo estrat?gico a avalia??o e compara??o de diferentes arquiteturas de redes intrachip atrav?s de uma plataforma de avalia??o unificada. Adota-se Nocbench, uma plataforma recente, j? validada em alguns contextos e proposta como um padr?o para a avalia??o de redes intrachip. O m?todo de avalia??o empregado baseia-se na simula??o de redes e utiliza como entrada modelos de tr?fego e de computa??o descritos sob a forma de traces, ambos extra?dos de aplica??es reais. As principais contribui??es do trabalho residem: (i) na proposta de diversas melhorias para a plataforma escolhida; (ii) no desenvolvimento de m?dulos para a integra??o das redes Hermes HS, Hermes OO, Hermes TB, Hermes VC e YeaHdo grupo de pesquisa do Autor ? plataforma em quest?o; (iii) no aprimoramento do processo de avalia??o de desempenho da plataforma, atrav?s da inclus?o de m?tricas comumente utilizadas para comparar redes intrachip, incluindo: lat?ncia, vaz?oe jitter. Um conjunto de experimentos valida as contribui??es e demonstra o uso da plataforma Nocbench como uma ferramenta ?til na compara??o de redes intrachip de origens diversas.

L’augmentation de la taille des réseaux actuels ainsi que de la diversité des applications qui les utilisent font que les architectures de calcul traditionnelles deviennent limitées. En effet, les architectures purement logicielles ne permettent pas de tenir les débits en jeu, tandis que celles purement matérielles n’offrent pas assez de flexibilité pour répondre à la diversité des applications. Ainsi, l’utilisation de solutions de type matériel programmable, en particulier les Field Programmable Gate Arrays (FPGAs), a été envisagée. En effet, ces architectures sont souvent considérées comme un bon compromis entre performances et flexibilité, notamment grâce à la technique de Reconfiguration Dynamique Partielle (RDP), qui permet de modifier le comportement d’une partie du circuit pendant l’exécution. Cependant, cette technique peut présenter des inconvénients lorsqu’elle est utilisée de manière intensive, en particulier au niveau du stockage des fichiers de configuration, appelés bitstreams. Pour palier ce problème, il est possible d’utiliser la relocation de bitstreams, permettant de réduire le nombre de fichiers de configuration. Cependant cette technique est fastidieuse et exige des connaissances pointues dans les FPGAs. Un flot de conception entièrement automatisé a donc été développé dans le but de simplifier son utilisation.Pour permettre une flexibilité sur l’enchaînement des traitements effectués, une architecture de communication flexible supportant des hauts débits est également nécessaire. Ainsi, l’étude de Network-on-Chips dédiés aux circuits reconfigurables et au traitements réseaux à haut débit.Enfin, un cas d’étude a été mené pour valider notre approche. / The increase in both size and diversity of applications regarding modern networks is making traditional computing architectures limited. Indeed, purely software architectures can not sustain typical throughputs, while purely hardware ones severely lack the flexibility needed to adapt to the diversity of applications. Thus, the investigation of programmable hardware, such as Field Programmable Gate Arrays (FPGAs), has been done. These architectures are indeed usually considered as a good tradeoff between performance and flexibility, mainly thanks to the Dynamic Partial Reconfiguration (DPR), which allows to reconfigure a part of the design during run-time.However, this technique can have several drawbacks, especially regarding the storing of the configuration files, called bitstreams. To solve this issue, bitstream relocation can be deployed, which allows to decrease the number of configuration files required. However, this technique is long, error-prone, and requires specific knowledge inFPGAs. A fully automated design flow has been developped to ease the use of this technique. In order to provide flexibility regarding the sequence of treatments to be done on our architecture, a flexible and high-throughput communication structure is required. Thus, a Network-on-Chips study and characterization has been done accordingly to network processing and bitstream relocation properties. Finally, a case study has been developed in order to validate our approach.