A complete analog front-end for portable ECG systems in 65nm technology was modeled and simulated using Cadence Virtuoso. All the required components for the AFE was incorporated into the continuous-time loop filter of a 10-bit ADC. By varying the effective transconductance of the input OTA, preamplification of the input signal was achieved. The required filtering is achieved through the ADC's own loop filter and through digital post-filtering. The ADC meets the IEC60601-2-47 standard. This simple, minimal and digitally assisted converter achieve some attractive features by dynamically adapting the programmable signal gain of the first integrator to keep the output signal range at a more constant level where the SNDR is sufficiently high.The ADC has a 100Hz bandwidth, achieves an ENOB of over 9.4 bits at a power consumption of 3.6 uWatts. The input referred noise ranges from 2.7uV(RMS) to 18.7uV(RMS) depending on gain setting. The estimated area consumption is about 0.2mm2.