Graduation date: 1999

A new second order accurate nonuniform grid spacing technique which does not depend on supraconvergence is developed for Finite Difference Time Domain (FDTD) simulation of general three dimensional structures. The technique is useful for FDTD simulations of systems which require finer details in small regions of the simulation space by providing the ability to utilize nonuniform grid spacing. The stability conditions of the new technique are derived and shown to be consistent with uniform grid formulation and the accuracy of the technique is investigated and shown to be second order. The advantage of the new technique is that it allows for greater simulation detail while reducing the computational and memory requirements compared to the current uniform grid FDTD techniques. Additionally, the derivation of the expressions associated with the inclusion of material properties in the FDTD simulation with nonuniform grids is presented allowing for the development of a nonuniform FDTD simulator for general lossy 3D systems associated with on and off chip interconnects, electronic packages and microwave circuits. In order to illustrate the utility of this simulator, time domain electromagnetic simulation of a 3-D lossy interconnect structure associated with a generic surface mount IC package is presented. The time domain currents and fields are computed in the structure to investigate ground bounce, signal degradation, and crosstalk associated with the interconnects and packaging structure. The supply plane conductivities are included in the simulation allowing the observation of the current densities in the power/ground planes as a function of time. Finally, the FDTD simulation tool is proposed and used as a Virtual TDR (V-TDR) to extract the circuit models associated with complex 3D structures. The time domain response of a multiport structure is used to extract the equivalent circuit parameters to characterize the multiport by using the multiport time domain reflection (TDR) based general deconvolution algorithm. Examples of coupled interconnects and transmission lines are presented to illustrate this technique. / Graduation date: 1997

The application of the personal computer in the area of real-time process control is investigated. Background information is provided regarding factory automation and process control. The current use of the PC in the factory for data acquisition is presented along with an explanation of the advantages and disadvantages associated with extending the use of the PC to real-time process control. The use of interrupt-driven and polled I/O to obtain real-time response is investigated and contrasted with the use of a real-time operating system. A unique compilation of information provides guidelines for selecting an implementation method for real-time control. Experimental work is performed to evaluate the access time and latency periods for the hard drive, video monitor, and I/O devices operating in a DOS environment. The execution speeds of C and assembly language programs are investigated. A method to estimate the performance of a real-time control system using polled or interrupt-driven I/O is developed. / Graduation date: 1997

The purpose of this study is to develop accuracy enhancement techniques for the Time Domain Reflection/Transmission (TDR/T) measurements including the analysis of the error sources for the Enhanced Accuracy TDR/T (EA-TDR/T). These TDR/T techniques are used for IC and IC package interconnect characterization and equivalent circuit model extraction, which are important for evaluating the overall system performance in today's digital IC design. The frequency domain error correction has been used to get parameters for a Device Under Test (DUT) from time domain measurements. The same technique can be used as an intermediate step for obtaining the EA-TDR/T. Careful choice of the acquisition window and precise alignment of the DUT and calibration standard waveforms are necessary to get the accuracy enhancement for the TDR/T. Improved FFT techniques are used in order to recover the actual spectra of the step-like time domain waveforms acquired with an acquisition window with a finite time length. The EA-TDR/T waveform are recovered from error corrected frequency domain parameters of the DUT by launching an ideal excitation at the DUT and finding the response. The rise time of the ideal excitation can be faster than that of the physical excitation in the measurement system. However, excessive high-frequency noise can enter the system if the rise time of the ideal excitation is chosen to be too high. The resulting EA-TDR/T waveforms show significantly less aberrations than the conventional TDR/T waveforms, hence allow us to extract accurate equivalent circuit model for the DUT, which in our case is IC interconnects. / Graduation date: 1995

The improved accuracy of Time Domain Reflection and Transmission (TDR/T) measurements made possible by the calibration process known as Time Domain Network Analysis (TDNA) is applied to the problem of characterization and modeling of electronic interconnect and packaging structures. TDNA uses measurements of known and partially known calibration standards to characterize the measurement system allowing for the correction of the raw measurements of an unknown network to eliminate the effects of system non-idealities and resulting in a significant improvement of the measurement quality. The correction process is shown to be analogous to the well established Frequency Domain Vector Network Analyzer calibrations and to have the same capabilities for high precision metrology applications. Methods are developed to extract electrical circuit models from time domain measurements of lossless, nonuniform, multiconductor transmission lines for two broad classes of structures. Although unique solutions are not feasible for general structures that scatter the propagating wave-front, approximate solutions have been identified using the assumption of a single velocity wave-front, the case for homogeneous media. For structures with identical lines, such as a parallel line bus structure, the propagation behavior (eigenvector matrix) is determined only by the number of conductors, N, and is therefore known a priori for the entire structure allowing decoupling of the system into N orthogonal nonuniform transmission lines. Circuit models have been developed for these decoupled nonuniform lines as well as for the equal modal velocity assumption which relies on a matrix impedance profile to fully describe the system. The implications of non-ideal grounding of interconnection circuits is explored. Traditional lumped element methods for modeling these effects are examined and typical examples where distributed circuit models are necessary to adequately describe the system are identified. Techniques for examining power-planes and substrate connections in integrated circuits and integrated circuit packages using the distributed ground model are presented. Novel circuit design methods to circumvent the limitations imposed by non-ideal grounds and nonzero length transmission structures are also proposed. / Graduation date: 1994

This paper describes a system for high resolution video conferencing. A number of camcorders are used to capture the video, which are then mosaiced to generate a wide angle panoramic view. Furthermore this system is made “real-time” by detecting changes and updating them on the mosaic. This system can be deployed on a single machine or on a cluster for better performance. It is also scalable and shows a good real-time performance. The main application for this system is videoconferencing for distance learning but it can be used for any high resolution broadcasting. / Singapore-MIT Alliance (SMA)

Neurturin (NTN) belongs to the glial cell-line derived neurotrophic factor (GDNF) family of growth factors. Both NTN and GDNF have been shown to potently prevent the degeneration of dopaminergic neuron in vitro and in vivo. The GDNF family receptor alpha 2 (GFRα-2) is the preferred receptor for NTN. In addition to the known full-length isoform (GFRα-2a), we have previously reported the isolation of two novel alternatively spliced isoforms (GFRα-2b and GFRα-2c). The expression levels of these isoforms have yet to be quantified and the functional properties determined. In this report, we have developed a real time polymerase chain reaction (PCR) using SYBR Green I to detect the expression levels of the three splice variants (GFRα-2a, GFRα-2b and GFRα-2c) in murine tissues. Both GFRα-2a and GFRα-2c were expressed at similar levels in all tissues examined. GFRα-2b was found to be 10 fold lower in expression. All three isoforms activated MAPK (ERK1/2) and Akt. Transcriptional profiling with DNA microarrays demonstrated that the spliced isoforms do not share similar profiles. In conclusion, we have now shown the expression levels of the spliced variants. All three isoforms are functional. However, each isoform appeared to have unique transcriptional profiles when activated. / Singapore-MIT Alliance (SMA)

We present a faster implementation of the polynomial time primal simplex algorithm due to Orlin [23]. His algorithm requires O(nm min{log(nC), m log n}) pivots and O(n2 m ??n{log nC, m log n}) time. The bottleneck operations in his algorithm are performing the relabeling operations on nodes, selecting entering arcs for pivots, and performing the pivots. We show how to speed up these operations so as to yield an algorithm whose running time is O(nm. log n) per scaling phase. We show how to extend the dynamic-tree data-structure in order to implement these algorithms. The extension may possibly have other applications as well.

This report describes Processor Coupling, a mechanism for controlling multiple ALUs on a single integrated circuit to exploit both instruction-level and inter-thread parallelism. A compiler statically schedules individual threads to discover available intra-thread instruction-level parallelism. The runtime scheduling mechanism interleaves threads, exploiting inter-thread parallelism to maintain high ALU utilization. ALUs are assigned to threads on a cycle byscycle basis, and several threads can be active concurrently. Simulation results show that Processor Coupling performs well both on single threaded and multi-threaded applications. The experiments address the effects of memory latencies, function unit latencies, and communication bandwidth between function units.

Thesis (Ph. D.)--Lehigh University, 2006. / Includes vita. Includes bibliographical references (leaves 284-293).