<p>This master's thesis deals with timing effects in complex on chip systems. It is written in cooperation with the research and development centre of Infineon Technologies. </p><p>One primary goal of all integrated circuit designers is to make the chips as small as possible. In deep sub micron designs timing effects like crosstalk have severe impact on the functionality of the chip. Therefore, accurate timing analyses must be made before the chip is ready for manufacturing. Otherwise the production yield can be reduced drastically. A case study on timing analysis with the 0.13 µm technology is made on the bus system of the device S-GOLD. </p><p>The computer-based program PrimeTime is used to carry out the timing analysis. During the evolution of 0.13 µm technology three design packages have been developed to characterize the timing. Two releases of SGOLD have been designed based on the first and the second design package. The different design packages were compared, with and without pin capacitance variations, on chip variations and crosstalk. Furthermore the two releases are compared. The result from the analysis tool may not correlate well with what you see on the manufactured chips. In order to investigate the correlation, some tests were finally performed on an evaluation board. </p><p>The results from the timing analysis are as expected. The second netlist version is better optimized than the first one. Design package three is most pessimistic among the three design packages. Design package one is most optimistic and does not match the real performance. Both design package two and three fit to the real performance well. Among the three design packages, design package three fits the real performance best.</p>

This master's thesis deals with timing effects in complex on chip systems. It is written in cooperation with the research and development centre of Infineon Technologies. One primary goal of all integrated circuit designers is to make the chips as small as possible. In deep sub micron designs timing effects like crosstalk have severe impact on the functionality of the chip. Therefore, accurate timing analyses must be made before the chip is ready for manufacturing. Otherwise the production yield can be reduced drastically. A case study on timing analysis with the 0.13 µm technology is made on the bus system of the device S-GOLD. The computer-based program PrimeTime is used to carry out the timing analysis. During the evolution of 0.13 µm technology three design packages have been developed to characterize the timing. Two releases of SGOLD have been designed based on the first and the second design package. The different design packages were compared, with and without pin capacitance variations, on chip variations and crosstalk. Furthermore the two releases are compared. The result from the analysis tool may not correlate well with what you see on the manufactured chips. In order to investigate the correlation, some tests were finally performed on an evaluation board. The results from the timing analysis are as expected. The second netlist version is better optimized than the first one. Design package three is most pessimistic among the three design packages. Design package one is most optimistic and does not match the real performance. Both design package two and three fit to the real performance well. Among the three design packages, design package three fits the real performance best.