FPGA devices are an important component in many modern devices. This means that it is important that VLSI designers have a thorough knowledge of how to optimize designs for FPGAs. While the design flows for ASICs and FPGAs are similar, there are many differences as well due to the limitations inherent in FPGA devices. To be able to use an FPGA efficiently it is important to be aware of both the strengths and oweaknesses of FPGAs. If an FPGA design should be ported to an ASIC at a later stage it is also important to take this into account early in the design cycle so that the ASIC port will be efficient. This thesis investigates how to optimize a design for an FPGA through a number of case studies of important SoC components. One of these case studies discusses high speed processors and the tradeoffs that are necessary when constructing very high speed processors in FPGAs. The processor has a maximum clock frequency of 357~MHz in a Xilinx Virtex-4 devices of the fastest speedgrade, which is significantly higher than Xilinx' own processor in the same FPGA. Another case study investigates floating point datapaths and describes how a floating point adder and multiplier can be efficiently implemented in an FPGA. The final case study investigates Network-on-Chip architectures and how these can be optimized for FPGAs. The main focus is on packet switched architectures, but a circuit switched architecture optimized for FPGAs is also investigated. All of these case studies also contain information about potential pitfalls when porting designs optimized for an FPGA to an ASIC. The focus in this case is on systems where initial low volume production will be using FPGAs while still keeping the option open to port the design to an ASIC if the demand is high. This information will also be useful for designers who want to create IP cores that can be efficiently mapped to both FPGAs and ASICs. Finally, a framework is also presented which allows for the creation of custom backend tools for the Xilinx design flow. The framework is already useful for some tasks, but the main reason for including it is to inspire researchers and developers to use this powerful ability in their own design tools.

A técnica de sinterização por plasma, também conhecida como processo SPS (Spark Plasma Sintering), é um processo para consolidação e sinterização de pós, em que corrente elétrica alternada pulsada e pressão de compactação são aplicadas simultaneamente aos componentes ferramentais (molde, punções, etc.). O molde utilizado neste processo tradicionalmente é cilíndrico, composto por grafite e permite a fabricação de amostras com geometria circular. Esse processo também possibilita a sinterização de um grande número de materiais, em especial, Materiais com Gradação Funcional (MGF). Tendo em vista os aspectos de geometria e composição da amostra, um projeto de otimização de moldes pode ser desenvolvido visando a fabricação de amostras com geometrias e gradação complexas. Com isso, é possível adequar a geometria do molde ao formato e composição da amostra que se deseja sinterizar, visando uma sinterização uniforme. Portanto, o objetivo deste trabalho é o desenvolvimento de uma metodologia para projetos de moldes utilizados na sinterização por plasma. Esta metodologia consiste na implementação de um algoritmo de otimização baseado no Método de Otimização Topológica (MOT), considerando três tipos de abordagem: a primeira abordagem, a qual visa a geometria da amostra, busca obter um molde prismático considerando amostras com geometria arbitrária, como por exemplo quadrada, triangular ou em cruz, com o objetivo de uniformizar o campo de temperaturas na amostra: na segunda abordagem, que considera moldes para a fabricação de amostras (MGF, os moldes podem ser projetados de modo a produzirem um gradiente de temperatura, na direção axial, através da variação da espessura da parede do molde; a terceira abordagem considera um molde constituído por material compósito. Nesta última abordagem é proposto um novo conceito de molde, onde se busca trabalhar não apenas com a geometria, como também com a microestrutura do molde dada por um material anisotrópico. Para a implementação do algoritmo de otimização, um modelo computacional baseado no Método dos Elementos Finitos (MEF), é desenvolvido considerando o processo SPS como um problema de acoplamento eletrotérmico. Na implementação do MOT utiliza-se um modelo de material baseado no SIMP (Solid Isotropic Material with Penalization) e Programação Linear Sequencial (PLS) para resolver o problema de otimização do molde. Todo algoritmo de otimização é implementado na linguagem própria do ambiente Matlab® e o pós-processamento, para verificação e validação dos resultados, é executado no software comercial Comsol®. / The Spark Plasma Sintering (SPS) technique is a powder consolidating and sintering process, in which pulsed DC electric current and pressure loads are applied simultaneously in the tool system components (graphite die, punchers, etc.) in order to perform the sintering process. Generally, a cylindrical graphite die is used for circular samples manufacturing and through this process the sinterization of a large number of materials, including Functionally Graded Materials (FGM), is possible. Considering the geometry and sample material aspects, an optimization die design technique can be developed based on the manufacturing of samples with complex geometry and gradation. Thus, it is possible to adjust the die geometry to the sample geometry or gradation in order to achieve a uniform sinterization. Therefore, the aim of this work is the development of a methodology to be applied in the design of dies used in SPS sintering process. This methodology consists of implementing an optimization algorithm based on the Topology Optimization Method (TOM), considering three approaches: in the first one a prismatic die is designed to process a sample with arbitrary geometry, for example square, triangular and cross sample; in the second approach the change of the die wall thickness is considered to achieve a predefined temperature gradient in the gradation direction of MGF samples and the third approach the same previous objective is considered, however the focus is the optimization of thermal conductive fibers. In the latest approach, a new die concept is proposed, where the objective is to optimize not only the die geometry but he microstructure considering a die composed by an anisotropic material. T implement the optimization algorithm a computational model based on the Finite Element Method (FEM) is developed considering the SPS process as an electrothermal coupled problem. In the TOM implementation a material model based on SIMP (Solid Isotropic Material with Penalization) is adopted and the Sequential Linear Programming is used to solve the optimization problem. The optimization algorithm is implemented using the Matlab® environment and the pos-processing, for verification and validation of the obtained results is carried out by using Comsol®.

Please read the abstract in the section 00front of this document / Dissertation (MSc)--University of Pretoria, 2005. / Computer Science / unrestricted

Programming languages like Python, JavaScript, and Ruby are becoming increasingly popular due to their dynamic capabilities. These languages are often much easier to learn than other, statically type checked, languages such as C++ or Rust. Unfortunately, these dynamic languages come at the cost of losing compile-time optimizations. Python is arguably the most popular language for data scientists and researchers in the artificial intelligence and machine learning communities. As this research becomes increasingly popular, and the problems these researchers face become increasingly computationally expensive, questions are being raised about the performance of languages like Python. Language features found in Python, more specifically dynamic typing and run-time modification of object attributes, preclude common static analysis optimizations that often yield improved performance. This thesis attempts to quantify the cost of dynamic features in Python. Namely, the run-time modification of objects and scope as well as the dynamic type system. We introduce Cannoli, a Python 3.6.5 compiler that enforces restrictions on the language to enable opportunities for optimization. The Python code is compiled into an intermediate representation, Rust, which is further compiled and optimized by the Rust pipeline. We show that the analyzed features cause a significant reduction in performance and we quantify the cost of these features for language designers to consider.

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Agda is a dependently-typed programming language and theorem prover, supporting proof construction in a functional programming style. Due to its incredibly flexible concrete syntax and support for Unicode identifiers, Agda can be used to construct elegant and expressive proofs in a format that is understandable even to those unfamiliar with the tool. However, the semantics of Agda is lacking resource guarantees of the kind that Haskell programmers are used to with lazy evaluation, where multiple uses of function arguments and let-bound variables still result in the corresponding expressions to be evaluated at most once. With the current compiler backends of Agda, a mathematically-natural way to structure programs therefore frequently results in inefficient compiled programs, where the run-time complexity can be exponentional in cases where corresponding Haskell code executes in linear time. This makes a highly-optimised compiler backend a particularly essential tool for practical development with Agda. The main contributions of this thesis are a series of compiler optimisations that inlines simple projections, removes some expressions with trivial evaluations that can be statically inferred, and reduces the need for repeated evaluations of the same expressions by increasing sharing. We developed transformations that focus on the inherent “loss” of sharing that is frequently the result of compiling Agda programs. Where an Agda developer may imagine that value sharing should exist in the generated Haskell code, it often does not. We present several optimising transformations that re-introduce some of this “lost” sharing without affecting the type-theoretic semantics, then apply these optimisations to several typical Agda applications to examine the memory allocation and execution time effects. In measuring the effects of these optimisations on Agda code we show that overall improvements in runtime on the order of 10-20% are possible. We hope that the development and discussion of these optimisations is useful to the Agda developer community, and may be helpful for future contributors interested in implementing new optimisations for Agda. / Thesis / Master of Science (MSc)

Thermal management is one of many critical tasks in the design of power electronic systems. It has become increasingly important as a result of the introduction of high power density and integrated modules. It has also been realized that higher temperatures do affect reliability due to a variety of physical failure mechanisms that involve thermal stresses and material degradation. Therefore, it is important to consider temperature as design parameter in developing power electronic modules. The NSF Center for Power Electronics System (CPES) at Virginia Tech previously developed a first generation (Gen-I) active Integrated Power Electronics Module (IPEM). This module represents CPES's approach to design a standard power electronic module with low labor and material costs and improved reliability compared to industrial Intelligent Power Modules (IPM). A preliminary Generation II (Gen-II.A) active IPEM was built using embedded power technology, which removes the wire bonds from the Gen-I IPEM. In this module, the three primary heat-generating devices are placed on a direct bonded copper substrate in a multi-chip module format. The overall goal of this research effort was to optimize the thermal performance of this Gen-II.A IPEM. To achieve this goal, a detailed three-dimensional active IPEM was modeled using the thermal-fluid analysis program ESC in I-DEAS to study the thermal performance of the Gen-II.A IPEM. Several design variables including the ceramic material, the ceramic thickness, and the thickness of the heat spreader were modeled to optimize IPEM geometric design and to improve the thermal performance while reducing the footprint. Input variables such as power loss and interface material thicknesses were studied in a sensitivity and uncertainty analysis. Other design constraints such as electrical design and packaging technology were also considered in the thermal optimization of the design. A new active IPEM design named Gen-II.C was achieved with reduced-size and improved thermal and electrical performance. The success of the new design will enable the replacement of discrete components in a front-end DC/DC converter by this standard module with the best thermal and electrical performance. Future improvements can be achieved by replacing the current silicon chip with a higher thermal-conductivity material, such as silicon carbide, as the power density increases, and by, exploring other possible cooling techniques. / Master of Science

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