In this thesis, we develop an automatic hardware synthesizer for multiplier-based arithmetic functions such as parallel multipliers/multiplier-accumulator/inner-product calculator. The synthesizer is divided into two major phases. In the first phase called pre-layout netlist generation, the synthesizer generates the gate-level verilog codes and the corresponding test fixture file for pre-layout simulation. The second phase, called layout-generation, is to produce the CIF file of final physical layout based on the gate-level netlist generated in the first phase. The thesis focuses on the first phase. The irregular connection of the Wallace tree in the parallel multiplier is optimized in order to reduce the overall delay and power. In addition to the conventional 3:2 couter that is usually included in standard cell library, our synthesizer can select other different compression elements that are full-custom designed using pass-transistor logic. We also propose several methods to partition the final addition part of the parallel multiplier into several regions in order to further reduce the critical path delay and the area cost. Thus, our multiplier generator combines the advantages of three basic design approaches: high-level synthesis, cell-based design and full-custom design along with area and power optimization.

No / A new scheme is presented for partitioning a network having a specific number of nodes and degree of connectivity such that the number of operations required to find a constrained path between a source node and destination node, averaged over all source-destination pairs, is minimised. The scheme can speed up the routing function, possibly by orders of magnitude under favourable conditions, at the cost of a sub-optimal solution.

No / This paper presents a new partitioning strategy with the objective of increasing scalability by reducing computational effort of routing in networks. The original network is partitioned into blocks (subnetworks) so that there is a bi-directional link between any two blocks. When there is a connection request between a pair of nodes, if the nodes are in the same block, we only use the small single block to derive routings. Otherwise we combine the two blocks where the two nodes locate and in this way the whole network will never be used. The strategy is generic in that it can be used in any underlying routing algorithms in the network layer and can be applied to any networks with fixed topology such as fixed wired subnetworks of the Internet. The performance of this strategy has been investigated by building a simulator in Java and a comparison with existing stochastic partitioning techniques is shown to give superior performance in terms of trade-off in blocking probability (the probability of failure to find a path between source and destination satisfying QoS constraints) and reduction of computational effort.