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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.

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A Broadband Passive Delay Line Structure in 0.18 Micron CMOS For A Gigabit Feed Forward Equalizer

Chandramouli, Soumya 01 November 2004 (has links)
This project focusses on the design of a high speed passive delay line for use in a Feed Forward Equalizer (FFE). The FFE is used to equalize a 20 Gbp/s throughput PAM-4 signal after transmission through a 20-inch FR4 backplane channel. Inductor electromagnetic simulations are used to design an inductor for use in the passive delay line and a lumped element inductor model is presented. Measurement results show performance of the delay line at 10 GSym/s.
Passive equalization
Passive delay lines
Inductor modeling

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