Thesis (PhD) - Swinburne University of Technology, Faculty of Engineering and Industrial Sciences, Centre for Micro-Photonics, 2008. / Submitted for the degree of Doctor of Philosophy, Centre for Micro-Photonics, Faculty of Engineering and Industrial Sciences, 2008. Typescript. Bibliography: p. 104-118.

Thesis (Ph. D.)--University of Oregon, 2008. / Typescript. Includes vita and abstract. Includes bibliographical references (leaves 147-163). Also available online in ProQuest, free to University of Oregon users.

Thesis (Ph. D.)--West Virginia University, 2001 / Title from document title page. Document formatted into pages; contains vii, 112 p. : ill. (some col.) Includes abstract. Includes bibliographical references.

Thesis (Ph. D.)--University of Chicago, Dept. of Chemistry. / Includes bibliographical references. Also available on the Internet.

Thesis (Ph. D.)--University of North Texas, August, 2008. / Title from title page display. Includes bibliographical references.

Thesis (Ph.D.)--University of Delaware, 2007. / Principal faculty advisor: Dennis W. Prather, Dept. of Electrical & Computer Engineering. Includes bibliographical references.

Thesis (M.Phil.)--Hong Kong University of Science and Technology, 2005. / Includes bibliographical references (leaves 77-82). Also available in electronic version.

Thesis (Ph. D.)--University of Texas at Austin, 2006. / Vita. Includes bibliographical references.

Silicon with its mature integration platform has brought electronic circuits to mass-market applications; silicon photonics will most probably follow this evolution. However, there are still many technological challenges to be addressed in order to realize silicon photonics technology. One of the key challenges is building a complete design environment interfaced with standard EDA tools; as in microelectronics, this would enable the creation of photonic libraries and photonic IP blocks. In this study, we focus on developing a physical verification (PV) flow for the silicon photonics technology.There are a number of components from the traditional CMOS IC physical verification world that can be borrowed. All, however, will require some modification due to the distinct nature of photonic circuits. We study the photonic circuit PV requirements, in comparison with those for traditional IC designs. The most significant limitation of current PV tools is to handle non- Manhattan layout designs. We adapt industrial standard PV tools to perform efficient and reliable design rule checking (DRC) that validates non-Manhattan like layout. We also propose methodologies and develop a layout versus schematic (LVS) checking flow specific to the non- Manhattan characteristics and photonic circuit verification requirements. The flow is capable of verifying photonic circuit layout implementation (or even manufactured silicon) with regard to the intended design. The developed flows are demonstrated with Mentor Graphics Pyxis design environment and Calibre® PV tool suit. As generic methodologies, they can also be in principle adopted in other EDA tool environments in order to verify the physical implementation of the photonic designs. Such a PV flow is essential for bringing the silicon photonics technology onto the real CMOS streamline. / La plate-forme d'intégration silicium est arrivée à maturité, et a amené les circuits intégrés électroniques (IC) aux applications du marché de masse ; la photonique sur silicium va suivre probablement cette évolution. Pourtant, il y a encore de nombreux défis technologiques à relever pour réaliser la technologie photonique sur silicium. Parmi les principaux défis, il est essentiel de se concentrer sur la construction d'un environnement de conception complet interfacé avec les outils EDA standards ; comme dans la microélectronique, il permettrait la création de librairies photoniques et des blocs IP photoniques. Dans cette étude, nous nous concentrons sur l’adaptation et le développement du flot de vérification physique (PV, ou « physical verification ») pour la conception photonique sur silicium.Il y a un certain nombre de concepts de PV existant pour le CMOS traditionnel qui peuvent être empruntés. Tous, cependant, nécessiteront quelques modifications en raison de la nature distincte du circuit photonique. Nous étudions les exigences de PV pour les circuits photoniques, en comparaison avec celles de la conception de circuits intégrés traditionnels. La limitation la plus importante des outils de PV actuels est de traiter les layout « non-Manhattan ». Nousadaptons des outils industriels standards pour effectuer un « design rule checking » (DRC) efficace et fiable qui valide les layout non-Manhattan. Nous proposons également des méthodologies et développons un flot « layout versus schematic » (LVS) spécifique aux caractéristiques non-Manhattan et aux exigences de vérification de circuits photoniques. Le flot est capable de vérifier le layout du circuit photonique (ou même le silicium fabriqué du circuit) en ce qui concerne la conception cible. Les flots développés sont démontrées avec les outils de Mentor Graphics – Pyxis (l’environnement de dessin) et Calibre® (les outils de PV). Comme les méthodologies génériques, ils peuvent aussi être en principe adoptés dans d'autres outils EDA afin d'effectuer la vérification de la réalisation de la conception du circuit photonique. Un tel flot de PV est essentiel pour amener la technologie photonique sur silicium sur la ligne de production réelle de CMOS.

Semiconductor quantum dots are promising candidates as bright, indistinguishable, single-photon sources---making them desirable for applications in quantum computing and quantum cryptography protocols. By embedding the quantum dots in III-V nanowires, the collection efficiency from the quantum dot is greatly increased. Our goal is to develop a platform that allows for the stable and efficient generation of single-photons on chip. This on-chip design offers an enhanced degree of stability and miniaturization, important in many applications involving the processing of quantum information. In this thesis, we demonstrate the efficient coupling of quantum light generated in a III-V photonic nanowire to a silicon-based photonic integrated circuit. We use high quality SiN waveguide devices fabricated by a foundry (LIGENTEC) to minimize coupling and propagation losses through the waveguide. A hybrid integration of these single-photon sources with a photonic integrated circuit is developed by employing a "pick & place" method which uses a nanomanipulator in a scanning electron microscope setup. By tailoring the nanowire geometry, we are able to maximize the efficient coupling between the optical mode of the photonic nanowire and an accompanying SiN waveguide through evanescent coupling. To determine the effectiveness of our integration method, we compare our hybrid devices with free-standing nanowires on their growth substrate. For each set, we measured the optical properties (brightness, spectral purity, lifetime, and single-photon purity) and efficiencies of the devices. We have shown that using tapered nanowires with embedded quantum dots coupled to on-chip photonic structures is a viable route for the fabrication of stable, high-efficiency, single-photon sources. Although the measured collection efficiencies from device to device were substantially different 9.6%~93%, we have found that the optical properties of the hybrid devices were hardly impacted from the transfer process. In fact, from the same nanowire that achieved 93% coupling efficiency, we were able to measure a single photon purity of 97%. By comparing the amount of emitted light collected from both ends of the nanowire (taper and base), we confirmed that the coupling efficiency of the devices have a strong dependence on the geometry of the nanowire as collection from the taper yielded count rates at least 10x greater than from the base. From our promising results, we can envision integrating the nanowire devices with different types of photonic structures such as ring resonators.