Digital filters play a key role in many DSP applications and FIR filters are usually selected because of their simplicity and stability against IIR filters.In this thesis eight architectures for multi-stream FIR filtering are studied. Primarily, three kinds of architectures are implemented and evaluated: one-toone mapping, time-multiplexed and pipeline interleaving. During implementation, practical considerations are taken into account such as implementation approach and number representation. Of interest is to see the performance comparison of different architectures, including area and power. The trade-off between area and power is an attractive topic for this work. Furthermore, the impact of the filter order and pipeline interleaving are studied.The result shows that the performance of different architectures differ a lot even with the same sample rate for each stream. It also shows that the performance of different architectures are affected by the filter order differently. Pipeline interleaving improves area utilization at the cost of rapid increment of power. Moreover, it has negative impact on the maximum working frequency.All the FIR filter architectures are synthesized in a 65nm technology.