A morfologia matemática fornece ferramentas poderosas para a realização de análise de imagens em baixo nível e tem encontrado aplicações em diversas áreas, tais como: visão robótica, inspeção visual, medicina, análise de textura, entre outras. Muitas dessas aplicações requerem processamento em tempo real e para sua execução de forma eficiente freqüentemente é utilizado hardware dedicado. Também, a tarefa de projetar operadores morfológicos manualmente para uma dada aplicação não é trivial na prática. A programação genética, que é um ramo relativamente novo em computação evolucionária, está se consolidando como um método promissor em aplicações envolvendo processamento de imagens digitais. Seu objetivo primordial é descobrir como os computadores podem aprender a resolver problemas sem, no entanto, serem programados para essa tarefa. Essa área ainda não foi muito explorada no contexto de construção automática de operadores morfológicos. Assim, neste trabalho, desenvolve-se e implementa-se uma arquitetura original, de baixo custo, reconfigurável por meio de instruções morfológicas e lógicas geradas automaticamente através de uma aproximação linear baseada em programação genética, visando-se o processamento morfológico de imagens em tempo real utilizando FPGAs de alta complexidade, com objetivos de filtragem, reconhecimento de padrões e emulação de filtros desconhecidos de softwares comerciais, para citar somente algumas aplicações. Exemplos de aplicações práticas envolvendo imagens binárias, em níveis de cinza e coloridas são fornecidos e seus resultados são comparados com outras formas de implementação. / Mathematical morphology supplies powerful tools for low level image analysis, with applications in robotic vision, visual inspection, medicine, texture analysis and many other areas. Many of the mentioned applications require dedicated hardware for real time execution. The task of designing manually morphological operators for a given application isnot always a trivial one. Genetic programming is a relatively new branch of evolutionary computing and it is consolidating as a promising method for applications of digital image processing. The main objective of genetic programming is to discover how computers can learn to solve problems without being programmed for that. In the literature little has been found about the automatic morphological operators construction using genetic programming. In this work, the development of an original reconfigurable architecture using logical and morphological instructions generated automatically by a linear approach based on genetic programming is presented. The developed architecture is based on Field Programmable Gate Arrays (FPGAs) and has among the possible applications, image filtering, pattern recognition and filter emulation. Binary, gray level and color image practical applications using the developed architecture are presented and the results are compared with other implementation techniques.

A morfologia matemática fornece ferramentas poderosas para a realização de análise de imagens em baixo nível e tem encontrado aplicações em diversas áreas, tais como: visão robótica, inspeção visual, medicina, análise de textura, entre outras. Muitas dessas aplicações requerem processamento em tempo real e para sua execução de forma eficiente freqüentemente é utilizado hardware dedicado. Também, a tarefa de projetar operadores morfológicos manualmente para uma dada aplicação não é trivial na prática. A programação genética, que é um ramo relativamente novo em computação evolucionária, está se consolidando como um método promissor em aplicações envolvendo processamento de imagens digitais. Seu objetivo primordial é descobrir como os computadores podem aprender a resolver problemas sem, no entanto, serem programados para essa tarefa. Essa área ainda não foi muito explorada no contexto de construção automática de operadores morfológicos. Assim, neste trabalho, desenvolve-se e implementa-se uma arquitetura original, de baixo custo, reconfigurável por meio de instruções morfológicas e lógicas geradas automaticamente através de uma aproximação linear baseada em programação genética, visando-se o processamento morfológico de imagens em tempo real utilizando FPGAs de alta complexidade, com objetivos de filtragem, reconhecimento de padrões e emulação de filtros desconhecidos de softwares comerciais, para citar somente algumas aplicações. Exemplos de aplicações práticas envolvendo imagens binárias, em níveis de cinza e coloridas são fornecidos e seus resultados são comparados com outras formas de implementação. / Mathematical morphology supplies powerful tools for low level image analysis, with applications in robotic vision, visual inspection, medicine, texture analysis and many other areas. Many of the mentioned applications require dedicated hardware for real time execution. The task of designing manually morphological operators for a given application isnot always a trivial one. Genetic programming is a relatively new branch of evolutionary computing and it is consolidating as a promising method for applications of digital image processing. The main objective of genetic programming is to discover how computers can learn to solve problems without being programmed for that. In the literature little has been found about the automatic morphological operators construction using genetic programming. In this work, the development of an original reconfigurable architecture using logical and morphological instructions generated automatically by a linear approach based on genetic programming is presented. The developed architecture is based on Field Programmable Gate Arrays (FPGAs) and has among the possible applications, image filtering, pattern recognition and filter emulation. Binary, gray level and color image practical applications using the developed architecture are presented and the results are compared with other implementation techniques.

With continuing research into quantum computing, current public key cryptographic algorithms such as RSA and ECC will become insecure. These algorithms are based on the difficulty of integer factorization or discrete logarithm problems, which are difficult to solve on classical computers but become easy with quantum computers. Because of this threat, government and industry are investigating new public key standards, based on mathematical assumptions that remain secure under quantum computing. This paper investigates methods of improving the area and performance of one of the proposed algorithms for key exchanges, "NewHope." We describe a pipelined FPGA implementation of NewHope512cpa which dramatically increases the throughput for a similar design area. Our pipelined encryption implementation achieves 652.2 Mbps and a 0.088 Mbps/LUT throughput-to-area (TPA) ratio, which are the best known results to date, and achieves an energy efficiency of 0.94 nJ/bit. This represents TPA and energy efficiency improvements of 10.05× and 8.58×, respectively, over a non-pipelined approach. Additionally, we investigate replacing the large SHAKE XOF (hash) function with a lightweight Trivium based PRNG, which reduces the area by 32% and improves energy efficiency by 30% for the pipelined encryption implementation, and which could be considered for future cipher specifications. / Master of Science / Cryptography is prevalent in almost every aspect of our lives. It is used to protect communication, banking information, and online transactions. Current cryptographic protections are built specifically upon public key encryption, which allows two people who have never communicated before to setup a secure communication channel. However, due to the nature of current cryptographic algorithms, the development of quantum computers will make it possible to break the algorithms that secure our communications. Because of this threat, new algorithms based on principles that stand up to quantum computing are being investigated to find a suitable alternative to secure our systems. These algorithms will need to be efficient in order to keep up with the demands of the ever growing internet. This paper investigates four hardware implementations of a proposed quantum-secure algorithm to explore ways to make designs more efficient. The improvements are valuable for high throughput applications, such as a server which must handle a large number of connections at once.

Face recognition is a field of biometrics that deals with identification of subjects based on features present in the images of their faces. The factors that make face recognition popular and favorite as compared to other biometric methods are easier operation and ability to identify subjects without their knowledge. With these features, face recognition has become an integral part of the present day security systems, targeting a smart and secure world. There are various factors that de ne the performance of a face recognition system. The most important among them are recognition accuracy of algorithm used and time taken for recognition. Recognition accuracy of the face recognition algorithm gets affected by changes in pose, facial expression and illumination along with occlusions in the images. There have been a number of algorithms proposed to enable recognition under these ambient changes. However, it has been hard to and a single algorithm that can efficiently recognize faces in all the above mentioned conditions. Moreover, achieving real time performance for most of the complex face recognition algorithms on embedded platforms has been a challenge. Real-time performance is highly preferred in critical applications such as identification of crime suspects in public. As available software solutions for FR have significantly large latency in recognizing individuals, they are not suitable for such critical real-time applications. This thesis focuses on real-time aspect of FR, where acceleration of the algorithms is achieved by means of parallel hardware architectures. The major contributions of this work are as follows. We target to design a face recognition system that can identify at most 30 faces in each frame of video at 15 frames per second, which amounts to 450 recognitions per second. In addition, we target to achieve good recognition accuracy along with scalability in terms of database size and input image resolutions. To design a system with these specifications, as a first step, we explore algorithms in literature and come up with a hybrid face recognition algorithm. This hybrid algorithm shows good recognition accuracy on face images with changes in illumination, pose and expressions, and also with occlusions. In addition the computations in the algorithm are modular in nature which are suitable for real-time realizations through parallel processing. The face recognition system consists of a face detection module to detect faces in the input image, which is followed by a face recognition module to identify the detected faces. There are well established algorithms and architectures for face detection in literature which can perform detection at 15 frames per second on video frames. Detected faces of different sizes need to be scaled to the size specified by the face recognition module. To meet the real-time constraints, we propose a hardware architecture for real-time bi-cubic convolution interpolation with dynamic scaling factors. To recognize the resized faces in real-time, a scalable parallel pipelined architecture is designed for the hybrid algorithm which can perform 450 recognitions per second on a database containing grayscale images of at most 450 classes on Virtex 6 FPGA. To provide flexibility and programmability, we extend this design to REDEFINE, a multi-core massively parallel reconfigurable architecture. In this design, we come up with FR specific programmable cores termed Scalable Unit for Region Evaluation (SURE) capable of performing modular computations in the hybrid face recognition algorithm. We replicate SUREs in each tile of REDEFINE to construct a face recognition module termed REDEFINE for Face Recognition using SURE Homogeneous Cores (REFRESH). There is a need to learn new unseen faces on-line in practical face recognition systems. Considering this, for real-time on-line learning of unseen face images, we design tiny processors termed VOP, Processor for Vector Operations. VOPs function as coprocessors to process elements under each tile of REDEFINE to accelerate micro vector operations appearing in the synaptic weight computations. We also explore deep neural networks which operate similar to the processing in human brain and capable of working on very large face databases. We explore the field of Random matrix theory to come up with a solution for synaptic weight initialization in deep neural networks for better classification . In addition, we perform design space exploration of hardware architecture for deep convolution networks and conclude with directions for future work.