No description available.

Thesis (Ph.D.)--Worcester Polytechnic Institute. / Keywords: composite Pd and Pd/Ag membranes, alloying, Pd/Ag barrier, intermetallic diffusion, bi-metal multi-layer BMML deposition, electroless plating kinetics, high temperature x-ray diffraction, aluminum hydroxide surface grading, porous sintered metal supports, hydrogen separation. Includes bibliographical references (leaves 279-296 ).

Thesis (M.S.)--Rochester Institute of Technology, 1994. / Typescript. Includes bibliographical references (leaves 134-137).

Thesis (M.S.)--Rochester Institute of Technology, 1991. / Typescript. Includes bibliographical references (leaves 165-168).

Thesis (Ph. D.)--University of Washington, 1998. / Vita. Includes bibliographical references (leaves 120-121).

Thesis (M.S.)--University of Wisconsin--Madison, 1966. / eContent provider-neutral record in process. Description based on print version record. Bibliography: l. 36-38.

Thesis (M.S.)--University of Wisconsin--Madison, 1966. / eContent provider-neutral record in process. Description based on print version record. Includes bibliographical references.

A detailed study, including the investigation of many methods of preparing a thallium sulphamate solution for thallium plating has been carried out. The optimum conditions for such a solution have been defined following experiments concerning the effect of different variables (polarisation, current density and additives). Satisfactory thallium electrodeposits have been obtained.

abstract: This work demonstrates a capable reverse pulse deposition methodology to influence gap fill behavior inside microvia along with a uniform deposit in the fine line patterned regions for substrate packaging applications. Interconnect circuitry in IC substrate packages comprises of stacked microvia that varies in depth from 20µm to 100µm with an aspect ratio of 0.5 to 1.5 and fine line patterns defined by photolithography. Photolithography defined pattern regions incorporate a wide variety of feature sizes including large circular pad structures with diameter of 20µm - 200µm, fine traces with varying widths of 3µm - 30µm and additional planar regions to define a IC substrate package. Electrodeposition of copper is performed to establish the desired circuit. Electrodeposition of copper in IC substrate applications holds certain unique challenges in that they require a low cost manufacturing process that enables a void-free gap fill inside the microvia along with uniform deposition of copper on exposed patterned regions. Deposition time scales to establish the desired metal thickness for such packages could range from several minutes to few hours. This work showcases a reverse pulse electrodeposition methodology that achieves void-free gap fill inside the microvia and uniform plating in FLS (Fine Lines and Spaces) regions with significantly higher deposition rates than traditional approaches. In order to achieve this capability, systematic experimental and simulation studies were performed. A strong correlation of independent parameters that govern the electrodeposition process such as bath temperature, reverse pulse plating parameters and the ratio of electrolyte concentrations is shown to the deposition kinetics and deposition uniformity in fine patterned regions and gap fill rate inside the microvia. Additionally, insight into the physics of via fill process is presented with secondary and tertiary current simulation efforts. Such efforts lead to show “smart” control of deposition rate at the top and bottom of via to avoid void formation. Finally, a parametric effect on grain size and the ensuing copper metallurgical characteristics of bulk copper is also shown to enable high reliability substrate packages for the IC packaging industry. / Dissertation/Thesis / Doctoral Dissertation Materials Science and Engineering 2018

LD2668 .T4 1966 C434 / Master of Science