Three improved operational amplifiers with low voltage and rail-to-rail constant are proposed. Two of the amplifiers are modified from the amplifier with a level shifting circuit. One improved amplifier has fewer devices, higher speed, and reduced area and the other improved amplifier is added an additional adjustable gain. The third amplifier is a floating voltage controlled voltage source (FVCVS) amplifier, which has reduced area and improved frequency response. The first two level shifting operational amplifiers are designed in a 0.5£gm UMC CMOS process. They use about half number of devices. The supply voltage is 1.3V, and the current consumes just only 22.6¢H of the original circuits. The unity gain frequency increases 56.8%. The slew rate, CMRR and PSRR are higher. The 2nd amplifier still has a rail-to-rail constant gm; however, the gm can be adjusted. The third amplifier uses the 0.35£gm UMC CMOS process with 1.2V operating voltage. The gain-bandwidth product is 53.8¢H larger than the original circuits. No frequency compensation is used and the devices are fewer. The results are obtained in HSPICE simulation.

Pavement is usually composed of aggregate, asphalt binder, and air voids; rigid pavement is built with hydraulic cement concrete; reinforced pavement contains steel. With these wide ranges of materials, different mechanical behaviors need to be defined in the pavement simulation. But so far, there is no research providing a comprehensive introduction and comparison between various contact models. This paper will give a detail exploration on the contact models that can be potentially used in DEM pavement simulation; in the analysis, it includes both a theoretical part, simulation results and computational time cost, which can reveal the fundamental mechanical behaviors for the models, and that can be a reference for researchers to choose a proper contact model. A new contact model—the power law viscoelastic contact model is implemented into software PFC 3D and is numerically verified. Unlike existing linear viscoelastic contact models, the approach presented in this thesis provides a detailed exploration of the contact model for thin film power-law creeping materials based on C.Y Chueng's work. This model is aimed at simulating the thin film asphalt layer between two aggregates, which is a common structure in asphalt mixtures. Experiments with specimens containing a thin film asphalt between two aggregates are employed to validate the new contact model. / Master of Science

Durant ces vingt dernières années l'émergence des technologies MEMS a rendu possible l'intégration de capteurs au sein de systèmes complexes de taille réduite. Quelques-uns de ces capteurs se retrouvent dans des dispositifs tels que les téléphones mobiles, GPSs, ordinateurs portables… Il existe néanmoins une contrainte majeure, quand à l’utilisation de capteurs dans les applications fonctionnant sur batterie : leurs «consommation». En effet du fait de cette contrainte la plus part des capteurs développés de nos jours sont basés sur des modes de transduction capacitif limitant ainsi la consommation mais par la même occasion complexifiant lourdement la conception de l’élément sensible. Cette complexité de réalisation de l’élément sensible se répercute donc sur le prix du produit final. Le meilleur moyen de diminuer le prix de revient d’un capteur est l’utilisation d’une technologie de transduction qui permet de diminuer la complexité structurelle du capteur. La transduction résistive répond bien à ce problème, cependant les structures de conditionnement de signal les plus utilisées dissipent une puissance excessive. Cette thèse propose donc l’étude d’une structure électronique faible bruit / faible consommation innovante (le pont Actif) permettant le conditionnement de signaux issus de capteurs résistifs. Les critères d’évaluation du pont actif sont ici le gain, le bruit intrinsèque de l’électronique (facteur limitant de la résolution) et, le plus important, la consommation globale du capteur (éléments sensible + électronique de traitement). / Since resistive sensors exist, the Wheatstone bridge has been the most commonly used conditioningand read-out architecture. Even with the development of MEMS in the last decade, the Wheatstonebridge remains the preferred solution to transpose a physical magnitude into the electrical domain assoon as a resistive transduction method is used. Nevertheless the Wheatstone bridge introduces amajor issue for low-power sensors, the dependence of resolution to power consumption. Moreover,the output signal is directly proportional to the supply voltage. Finally, power consumption is theprice to pay for high resolution in a Wheatstone bridge.Low-power requirement, in mobile applications, is probably one of the main reasons to explain whycapacitive transduction has been preferred for many MEMS. Indeed, even if the fabrication process isoften more complex than for resistive sensors, the power consumption of capacitive transduction isfar below the one of dissipative resistor-based sensors.In order to extend the potential application of resistive MEMS, a power-efficient interface circuit isrequired. My PhD thesis deals with the design and manufacturing of an innovative conditioning andread-out interface for resistive MEMS sensor. The proposed structure includes a digital offsetcompensation for robustness to process, voltage, temperature variations, and/or analog to digitalconversion. Results demonstrate good resolution to power consumption ratio and a good immunityto environmental parameters. Experimental results on a fully integrated CMOS/MEMS sensor finallydemonstrate the efficiency of this promising read-out architecture called The active bridge.

Artificial Neural Networks (ANNs) appear increasingly and routinely to gain popularity today, as they are being used in several diverse research fields and many different contexts, which may range from biological simulations and experiments on artificial neuronal models to machine learning models intended for industrial and engineering applications. One example is the recent success of Deep Learning architectures (e.g., Deep Belief Networks [DBN]), which appear in the spotlight of machine learning research, as they are capable of delivering state-of-the-art results in many domains. While the performance of such ANN architectures is greatly affected by their scale, their capacity for scalability both for training and during execution is limited by the increased power consumption and communication overheads, implicitly posing a limiting factor on their real-time performance. The on-going work on the design and construction of spike-based neuromorphic platforms offers an alternative for running large-scale neural networks, such as DBNs, with significantly lower power consumption and lower latencies, but has to overcome the hardware limitations and model specialisations imposed by these type of circuits. SpiNNaker is a novel massively parallel fully programmable and scalable architecture designed to enable real-time spiking neural network (SNN) simulations. These properties render SpiNNaker quite an attractive neuromorphic exploration platform for running large-scale ANNs, however, it is necessary to investigate thoroughly both its power requirements as well as its communication latencies. This research focusses on around two main aspects. First, it aims at characterising the power requirements and communication latencies of the SpiNNaker platform while running large-scale SNN simulations. The results of this investigation lead to the derivation of a power estimation model for the SpiNNaker system, a reduction of the overall power requirements and the characterisation of the intra- and inter-chip spike latencies. Then it focuses on a full characterisation of spiking DBNs, by developing a set of case studies in order to determine the impact of (a) the hardware bit precision; (b) the input noise; (c) weight variation; and (d) combinations of these on the classification performance of spiking DBNs for the problem of handwritten digit recognition. The results demonstrate that spiking DBNs can be realised on limited precision hardware platforms without drastic performance loss, and thus offer an excellent compromise between accuracy and low-power, low-latency execution. These studies intend to provide important guidelines for informing current and future efforts around developing custom large-scale digital and mixed-signal spiking neural network platforms.

The main outcome of this research is the development of a Probabilistic Impact Assessment methodology to comprehensively understand the effects of low carbon technologies (LCTs) in low voltage (LV) distribution networks and the potential solutions available to increase their adoption. The adoption of LCTs by domestic customers is an alternative to decreasing carbon emissions. Given that these customers are connected to LV distribution networks, these assets are likely to face the first impacts of LCTs. Thus, to quantify these problems a Monte Carlo-based Probabilistic Impact Assessment methodology is proposed in this Thesis. This methodology embeds the uncertainties related to four LCTs (PV, EHPs, µCHP and EVs). Penetration levels as a percentage of houses with a particular LCT, ranging from 0 to 100% in steps of 10%, are investigated. Five minute time-series profiles and three-phase four-wire LV networks are adopted. Performance metrics related to voltage and congestion are computed for each of the 100 simulations per penetration level. Given the probabilistic nature of the approach, results can be used by decision makers to determine the occurrence of problems according to an acceptable probability of technical issues. To implement the proposed methodology, electrical models of real LV networks and high resolution profiles for loads and LCTs are also developed. Due to the historic passive nature of LV circuits, many Distribution Network Operators (DNOs) have no model for them. In most cases, the information is limited to Geographic Information Systems (GIS) typically produced for asset management purposes and sometimes with connectivity issues. Hence, this Thesis develops a methodology to transform GIS data into suitable computer-based models. In addition, thousands of residential load, PV, µCHP, EHP and EV profiles are created. These daily profiles have a resolution of five minutes. To understand the average behaviour of LCTs and their relationship with load profiles, the average peak demand is calculated for different numbers of loads with and without each LCT.The Probabilistic Impact Assessment methodology is applied over 25 UK LV networks (i.e., 128 feeders) for the four LCTs under analysis. Findings show that about half of the studied feeders are capable of having 100% of the houses with a given LCT. A regression analysis is carried out per LCT, to identify the relationships between the first occurrence of problems and key feeder parameters (length, number of customers, etc.). These results can be translated into lookup tables that can help DNOs produce preliminary and quick estimates of the LCT impacts on a particular feeder without performing detailed studies. To increase the adoption of LCTs in the feeders with problems, four solutions are investigated: feeder reinforcement, three-phase connection of LCTs, loop connection of LV feeders and implementation of OLTCs (on-load tap changers) in LV networks. All these solutions are embedded in the Probabilistic Impact Assessment. The technical and economic benefits of each of the solutions are quantified for the 25 networks implemented.

This work deals with issues of design and optimize of an operational amplifiers using CMOS transistor models. The main focus of work is to propose a circuit suitable for low voltage applications with low power. The proposed circuit consists of sub-circuits, each of which must operate in the desired voltage range. Detailed design of input and output stages will reach range of rail-to-rail type with a minimum quiescent current.

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