Programmable self-assembly has been widely studied because of its capability to create ordered patterns from a group of multiple disordered agents without an external controller. To achieve this, assembly units must exhibit different characteristics: they need to be small, to have the ability to latch and unlatch, and low-power consumption. In addition, they need to be easily programmable and able to communicate with each other. This thesis presents an experimental robotic platform for programmable self-assembly. In this work, we build in the Usbot modular robotic cubes making use of their advantages and simplicity as its passive magnetic latching mechanism, and we endow them with communication capabilities. The system allows only local communication between the modules, specifically with the most recent linked neighbor cube. The transmission of the relevant cube data is performed by a pair of LED and ambient light sensors in a binary format. The different experiments demonstrate and compare distributed programmable self-assembly using various algorithms from the literature as Singleton and Lynchpin.

Les attaques en fautes (FA) et par canaux cachés (SCA), permettent de récupérer des données sensibles stockées dans des équipements cryptographiques, en exploitant une fuite d'information provenant de leur implémentation matérielle. Le but de cette thèse est donc de formuler un état de l'art des contre-mesures aux SCA adaptées aux FPGA, ainsi que d'implémenter celles qui seront retenues en minimisant les pertes de performance et de complexité. Le cas des algorithmes symétriques tel AES est spécialement étudié, révélant plusieurs faiblesses des contre-mesures habituelles (DPL et masquage) en terme de résistance et de coût. Trois nouvelles contre-mesures sont donc proposées: 1.Des stratégies de placement/routage équilibrés destinées à amélioré la résistance des DPL sur FPGA. 2.Un nouveau type de DPL appelée BCDL (Balanced Cell-based Dual-rail Logic) dont le but est de supprimer la plupart des vulnérabilités liées aux DPLs. BCDL est également résilient à la majeure partie des FA et optimisé pour les FPGA, ce qui induit des complexité et performance compétitives. 3. RSM (Rotating S-Box Masking), une nouvelle technique de masquage pour AES qui montre un haut niveau de performances et résistance pour une complexité réduite. Finalement, plusieurs nouvelles SCA sont présentées et évaluées. RC (Rank Corrector) est un algorithme permettant d'améliorer les autres SCA. La FPCA introduit un nouveau distingueur basée sur la PCA. Puis plusieurs combinaisons (distingueur et mesures) sont proposées et résultent en une diminution du nombre de trace nécessaire à l'attaque. / Side-Channel Analysis (SCA) and Fault Attacks (FA) are techniques to recover sensitive information in cryptographic systems by exploiting unintentional physical leakage, such as the power consumption. This thesis has two main goals: to draw a review of the state of the art of FPGA-compatible countermeasures against SCA and implement t the selected ones with the minimum area and performances overhead. Symmetrical algorithms, specially AES, are studied and several vulnerabilities of usual protections, namely Dual-rail with Precharge Logic (DPL) and masking are analysed, as well as the issue of performance and area overheads. In this context, three new countermeasures are considered: 1. Balance placement and routing (PAR) strategies aiming at enhancing existing DPLs robustness when implemented in modern FPGAs. 2. A new type of DPL called Balanced Cell-based Dual-railLogic (BCDL), to thwart most of the known DPL weaknesses. BCDL also possess a fault resilience mechanism and provides implementation optimisations on FPGA, achieving competitive performances and area overhead. 3. The Rotating S-Box Masking (RSM), a new masking technique for the AES that shows high leveles of robustness and performances while bringing a significant reduction of the area overhead. Finally, several new SCAs are presented and evaluated. Firstly the “Rank Corrector” a SCA enhancement algorithm. Secondly, The FPCA, introduces a novel SCA distinguisher based on the PCA. Then, combinations of either acquisition methods or SCA distinguishers are discussed and show significant decrease in the number of measurements required to perform a successful attack.

This thesis presents an approach for modeling and generating efficient hardware architectures using constraint programming techniques, targeting field programmable gate arrays (FPGAs). The focus of this thesis is the derivation of optimal or near-optimal schedules for streaming applications from data flow graphs (DFGs). The resulting schedules are then used to facilitate the architecture generation process. Most streaming applications, like digital singal processing (DSP) algorithms, are repetitive in nature: the same computation is performed on different data items. This repetitive nature of streaming applications can be used to expose additional parallelism available across different iterations, by creating multiple instances of the same computation. The replication of the single computation, when applied to high level synthesis (HLS), improves the performance of the design but requires additional area. The amount of additional area required for a replicated graph can be reduced through the use of pipelined functional units and the addition of some extra clock cycles beyond the critical path of the DFG. This thesis discusses the use of a constraint programming (CP)-based scheduler to generate optimal schedules based on designer-provided replication level and critical path relaxation. The scheduler is an integrated part of the design tool, called CHARGER, which analyzes the resulting schedules to allocate memory for storing intermediate data, creates the infrastructure necessary to efficiently execute the application, and finally generates a synthesizable Verilog/VHDL code for the controller. The performance of the architectures derived using the CP-based scheduler is compared with the architectures generated using a force directed scheduling (FDS)-based scheduler for algorithms selected from embedded/multimedia applications. The results show that our CP-based scheduler outperforms the FDS-based scheduler, both in terms of area and efficiency of the generated architectures. The results show average area saving of 39% and average performance improvement of 41%.

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Safety and mission critical systems are currently deployed in many different fields where there is a greater presence of high energy particles (e.g.\ aerospace). The use of field programmable gate arrays (FPGAs) within safety critical systems is becoming more prevalent due to the design and cost benefits their use provides. The effects of externally caused faults on these safety critical systems cannot be neglected. In particular, high energy particle striking a circuit can cause a voltage change in the circuit known as a soft error. The effects these soft errors will have on the circuit needs to be understood in order to ensure that the systems will function properly in the event soft errors do occur. In this thesis a tool is designed to facilitate the run-time injection of soft errors into a hardware circuit running on a FPGA. The tool allows for the control over the number of injections that can be performed and control over the rate that the injections will occur at. Additionally the tool records time stamps of when injections occur and time stamps of when errors are detected. This recorded data allows for the analysis of designs in conditions prone to soft errors. The implemented tool allows for design time parametrization and run time configuration, allowing a multitude of tests to be run for a single compiled design. The tool also eliminates the need for a host computer after configuration by generating the injection locations and times on the FPGA. Eliminating the host computer allows for faster testing when compared to other methods as data transfer times are greatly reduced. The implemented tool was run on classical examples of redundant structures, such as duplication with comparison and triple modular redundancy as well as a non-redundant structure to establish a baseline. The results of multiple tests run on each structure are analyzed to illustrate the uses of the tool and how the tool may be used to test other designs. / Thesis / Master of Applied Science (MASc)

Time-triggered communication is widely used throughout several industry do- mains, primarily for reliable and real-time capable data transfers. However, existing time-triggered technologies are designed for terrestrial usage and not directly applicable to space applications due to the harsh environment. In- stead, specific hardware must be developed to deal with thermal, mechanical, and especially radiation effects. SpaceWire, as an event-triggered communication technology, has been used for years in a large number of space missions. Its moderate complexity, her- itage, and transmission rates up to 400 MBits/s are one of the main ad- vantages and often without alternatives for on-board computing systems of spacecraft. At present, real-time data transfers are either achieved by prior- itization inside SpaceWire routers or by applying a simplified time-triggered approach. These solutions either imply problems if they are used inside dis- tributed on-board computing systems or in case of networks with more than a single router are required. This work provides a solution for the real-time problem by developing a novel clock synchronization approach. This approach is focused on being compatible with distributed system structures and allows time-triggered data transfers. A significant difference to existing technologies is the remote clock estimation by the use of pulses. They are transferred over the network and remove the need for latency accumulation, which allows the incorporation of standardized SpaceWire equipment. Additionally, local clocks are controlled decentralized and provide different correction capabilities in order to handle oscillator induced uncertainties. All these functionalities are provided by a developed Network Controller (NC), able to isolate the attached network and to control accesses. / Zeitgesteuerte Datenübertragung ist in vielen Industriezweigen weit verbreitet, primär für zuverlässige und echtzeitfähige Kommunikation. Bestehende Technologien sind jedoch für den terrestrischen Gebrauch konzipiert und aufgrund der rauen Umgebung nicht direkt auf Weltraumanwendungen anwendbar. Stattdessen wird spezielle Hardware entwickelt, um Strahlungseffekten zu widerstehen sowie thermischen und mechanischen Belastungen standzuhalten. SpaceWire wurde als ereignisgesteuerte Kommunikationstechnologie entwickelt und wird seit Jahren in einer Vielzahl von Weltraummissionen verwendet. Dessen erfolgreiche Verwendung, überschaubare Komplexität, und Übertragungsraten bis zu 400 MBit/s sind einige seiner Hauptvorteile. Derzeit werden Datenübertragungen in Echtzeit entweder durch Priorisierung innerhalb von SpaceWire Router erreicht, oder durch Anwendung von vereinfachten zeitgesteuerten Ansätzen. Diese Lösungen implizieren entweder Probleme in verteilten Systemarchitekturen oder in SpaceWire Netzwerken mit mehreren Routern. Diese Arbeit beschreibt eine Uhrensynchronisation, die bestimmte Eigenschaften von SpaceWire ausnutzt, um das Echtzeitproblem zu lösen. Der Ansatz ist dabei kompatibel mit verteilten Systemstrukturen und ermöglicht eine zeitgesteuerte Datenübertragung.

In recent years, Light-emitting Diodes (LEDs) have become a promising candidate for backlighting Liquid Crystal Displays [1] (LCDs). Compared with traditional Cold Cathode Fluorescent Lamps (CCFLs) technology, LEDs offer not only better visual quality, but also improved power efficiency. However, to fully utilized LEDs' capability requires dynamic independent control of individual LEDs, which remains as a challenging topic. A FPGA-based hardware system for LED backlight control is proposed in this work. We successfully achieve dynamic adjustment of any individual LED's intensity in each of the three color channels (Red, Green and Blue), in response to a real time incoming video stream. In computing LED intensity, four video content processing algorithms have been implemented and tested, including averaging, histogram equalization, LED zone pattern change detection and non-linear mapping. We also construct two versions of the system. The first employs an embedded processor which performs the above-mentioned algorithms on pre-processed video data; the second embodies the same functionality as the first on fixed hardware logic for better performance and power efficiency. The system servers as the backbone of a consolidated display, which yields better visual quality than common commercial displays, we build in collaboration with a group of researchers from CREOL at UCF.