Thesis (Ph. D.)--University of Washington, 2005. / Vita. Includes bibliographical references (leaves 168-172).

Zhou Lin. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2004. / Includes bibliographical references (leaves 50-53). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation --- p.1 / Chapter 1.2 --- Aims and Contribution --- p.3 / Chapter 1.3 --- Thesis Overview --- p.4 / Chapter 2 --- Field-Programmable Gate Array and Routing Algorithm in VPR --- p.6 / Chapter 2.1 --- Commercially Available FPGAs --- p.6 / Chapter 2.2 --- FPGA Logic Block Architecture --- p.7 / Chapter 2.2.1 --- Logic Block Functionality vs. FPGA Area-Efficiency --- p.7 / Chapter 2.2.2 --- Logic Block Functionality vs. FPGA Delay-Performance --- p.7 / Chapter 2.2.3 --- Lookup Table-Based FPGAs --- p.8 / Chapter 2.3 --- FPGA Routing Architecture --- p.8 / Chapter 2.4 --- Design Parameters of FPGA Routing Architecture --- p.10 / Chapter 2.5 --- CAD for FPGAs --- p.10 / Chapter 2.5.1 --- Synthesis and Logic Block Packing --- p.11 / Chapter 2.5.2 --- Placement --- p.11 / Chapter 2.5.3 --- Routing --- p.12 / Chapter 2.5.4 --- Delay Modelling --- p.13 / Chapter 2.5.5 --- Timing Analysis --- p.13 / Chapter 2.6 --- FPGA Programming Technologies --- p.13 / Chapter 2.7 --- Routing Algorithm in VPR --- p.14 / Chapter 2.7.1 --- Pathfinder Negotiated Congestion Algorithm --- p.14 / Chapter 2.7.2 --- Routing Algorithm Used by VPR --- p.16 / Chapter 3 --- Connection-Switch Box Design --- p.17 / Chapter 3.1 --- Introduction --- p.17 / Chapter 3.2 --- Connection-Switch Box Design Algorithm --- p.19 / Chapter 3.2.1 --- Connection between Logic Pins and Tracks --- p.20 / Chapter 3.2.2 --- Connection between Pad Pins and Tracks --- p.25 / Chapter 3.3 --- Switch Number Comparisons --- p.26 / Chapter 3.4 --- Experimental Results --- p.29 / Chapter 3.5 --- Summary --- p.32 / Chapter 4 --- Optimal MST-Based Graph Algorithm on FPGA Segmenta- tion Design --- p.37 / Chapter 4.1 --- Introduction --- p.37 / Chapter 4.2 --- MST-Based Graph Algorithm on FPGA Channel Segmentation Design --- p.39 / Chapter 4.2.1 --- Net Merging Problem of Row-Based FPGAs --- p.41 / Chapter 4.2.2 --- Extended Net Merging Problem of Symmetrical Array FPGAs --- p.44 / Chapter 4.3 --- Experimental Results --- p.46 / Chapter 4.4 --- Summary --- p.46 / Chapter 5 --- Conclusions --- p.48 / Bibliography --- p.50

Cheung Chak Chung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2001. / Includes bibliographical references (leaves 101-114). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgments --- p.iii / Vita --- p.v / Table of Contents --- p.vi / List of Figures --- p.x / List of Tables --- p.xiv / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation --- p.1 / Chapter 1.2 --- Aims and Contribution --- p.4 / Chapter 1.3 --- Thesis Overview --- p.5 / Chapter 2 --- VLSI Design Cycle --- p.6 / Chapter 2.1 --- Logic Synthesis --- p.7 / Chapter 2.1.1 --- Logic Minimization --- p.8 / Chapter 2.1.2 --- Technology Mapping --- p.8 / Chapter 2.1.3 --- Testability --- p.8 / Chapter 2.2 --- Physical Design Synthesis --- p.8 / Chapter 2.2.1 --- Partitioning --- p.9 / Chapter 2.2.2 --- Floorplanning & Placement --- p.10 / Chapter 2.2.3 --- Routing --- p.11 / Chapter 2.2.4 --- "Compaction, Extraction & Verification" --- p.12 / Chapter 2.2.5 --- Physical Design of FPGAs --- p.12 / Chapter 3 --- Alternative Wiring --- p.13 / Chapter 3.1 --- Introduction --- p.13 / Chapter 3.2 --- Notation and Definitions --- p.15 / Chapter 3.3 --- Application of Rewiring --- p.17 / Chapter 3.3.1 --- Logic Optimization --- p.17 / Chapter 3.3.2 --- Timing Optimization --- p.17 / Chapter 3.3.3 --- Circuit Partitioning and Routing --- p.18 / Chapter 3.4 --- Logic Optimization Analysis --- p.19 / Chapter 3.4.1 --- Global Flow Optimization --- p.19 / Chapter 3.4.2 --- OBDD Representation --- p.20 / Chapter 3.4.3 --- Automatic Test Pattern Generation (ATPG) --- p.22 / Chapter 3.4.4 --- Graph Based Alternative Wiring (GBAW) --- p.23 / Chapter 3.5 --- Augmented GBAW --- p.26 / Chapter 3.6 --- Logic Optimization by using GBAW --- p.28 / Chapter 3.7 --- Conclusions --- p.31 / Chapter 4 --- Multi-way Partitioning using Rewiring Techniques --- p.33 / Chapter 4.1 --- Introduction --- p.33 / Chapter 4.2 --- Circuit Partitioning Algorithm Analysis --- p.38 / Chapter 4.2.1 --- The Kernighan-Lin (KL) Algorithm --- p.39 / Chapter 4.2.2 --- The Fiduccia-Mattheyses (FM) Algorithm --- p.42 / Chapter 4.2.3 --- Geometric Representation Algorithm --- p.46 / Chapter 4.2.4 --- The Multi-level Partitioning Algorithm --- p.49 / Chapter 4.2.5 --- Hypergraph METIS - hMETIS --- p.51 / Chapter 4.3 --- The GBAW Partitioning Algorithm --- p.53 / Chapter 4.4 --- Experimental Results --- p.56 / Chapter 4.5 --- Conclusions --- p.58 / Chapter 5 --- Optimum FPGA Switch-Box Designs - HUSB --- p.62 / Chapter 5.1 --- Introduction --- p.62 / Chapter 5.2 --- Background and Definitions --- p.65 / Chapter 5.2.1 --- Routing Architectures --- p.65 / Chapter 5.2.2 --- Global Routing --- p.67 / Chapter 5.2.3 --- Detailed Routing --- p.67 / Chapter 5.3 --- FPGA Router Comparison --- p.69 / Chapter 5.3.1 --- CGE --- p.69 / Chapter 5.3.2 --- SEGA --- p.70 / Chapter 5.3.3 --- TRACER --- p.71 / Chapter 5.3.4 --- VPR --- p.72 / Chapter 5.4 --- Switch Box Design --- p.73 / Chapter 5.4.1 --- Disjoint type switch box (XC4000-type) --- p.73 / Chapter 5.4.2 --- Anti-symmetric switch box --- p.74 / Chapter 5.4.3 --- Universal Switch box --- p.74 / Chapter 5.4.4 --- Switch box Analysis --- p.75 / Chapter 5.5 --- Terminology --- p.77 / Chapter 5.6 --- "Hyper-universal (4, W)-design analysis" --- p.82 / Chapter 5.6.1 --- "H3 is an optimum (4, 3)-design" --- p.84 / Chapter 5.6.2 --- "H4 is an optimum (4,4)-design" --- p.88 / Chapter 5.6.3 --- "Hi is a hyper-universal (4, i)-design for i = 5,6,7" --- p.90 / Chapter 5.7 --- Experimental Results --- p.92 / Chapter 5.8 --- Conclusions --- p.95 / Chapter 6 --- Conclusions --- p.99 / Chapter 6.1 --- Thesis Summary --- p.99 / Chapter 6.2 --- Future work --- p.100 / Chapter 6.2.1 --- Alternative Wiring --- p.100 / Chapter 6.2.2 --- Partitioning Quality --- p.100 / Chapter 6.2.3 --- Routing Devices Studies --- p.100 / Bibliography --- p.101 / Chapter A --- 5xpl - Berkeley Logic Interchange Format (BLIF) --- p.115 / Chapter B --- Proof of some 2-local patterns --- p.122 / Chapter C --- Illustrations of FM algorithm --- p.124 / Chapter D --- HUSB Structures --- p.127 / Chapter E --- Primitive minimal 4-way global routing Structures --- p.132

No description available.

No description available.

Thesis (Ph. D.)--University of Washington, 2004. / Vita. Includes bibliographical references (leaves 95-104).

Thesis (Ph. D.)--University of Texas at Austin, 1998. / Vita. Includes bibliographical references (leaves 111-116). Available also in a digital version from Dissertation Abstracts.

Thesis (M.Eng.Sc.) - University of Queensland, 2002. / Includes bibliography.

Thesis (Ph. D.)--University of Washington, 2005. / Includes bibliographical references (leaves 129-132).

No description available.