Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009. / Committee Chair: Hasler, Paul; Committee Member: Anderson, David; Committee Member: Degertekin, F.; Committee Member: Ghovanloo, Maysam; Committee Member: Minch, Bradley. Part of the SMARTech Electronic Thesis and Dissertation Collection.

ITC/USA 2013 Conference Proceedings / The Forty-Ninth Annual International Telemetering Conference and Technical Exhibition / October 21-24, 2013 / Bally's Hotel & Convention Center, Las Vegas, NV / A field programmable gate array (FPGA) is used to decode Inter-Range Instrumentation Group (IRIG) time code for a PC-based Time-Space-Position Information (TSPI) acquisition. The FPGA architecture can latch time via an external event trigger or a programmable periodic internal event. By syncing time with an external IRIG Group Type B (IRIG-B) signal and using an 8 megahertz (MHz) internal clock, captured time has 125 nanosecond (ns) precision. A Range Instrumentation Control System (RICS) application utilizing the FPGA design to capture IRIG time is presented and test results show matching time accuracy when compared to commercial IRIG time capture hardware components.

published_or_final_version / abstract / Electrical and Electronic Engineering / Master / Master of Philosophy

Η μεγάλη εξάπλωση των δικτύων που βασίζονται στο Internet Protocol (IP) , έδωσε την ευκαιρία για χρήση του Διαδικτύου για μετάδοση φωνής , μέσω της τεχνολογίας Voice over IP(VoIP) , έναντι των παραδοσιακών δημοσίων τηλεφωνικών δικτύων (PSTN) . Το Session Initiation Protocol είναι το πρωτόκολλο σηματοδοσίας , που χρησιμοποιείται για τον έλεγχο συνόδων πολυμέσων , όπως κλήσεις φωνής ή βιντεοκλήσεις στα δίκτυα IP . Η χρησιμοποίηση του πρωτοκόλλου σε φορητές συσκευές , όπου η διαχείριση πόρων παίζει σπουδαίο ρόλο , δίνει το ερέθισμα για τη δημιουργία ειδικού υλικού που θα αποφορτίζει τον επεξεργαστή της συσκευής από τους απαιτητικούς ελέγχους που χρειάζονται για την δημιουργία μιας συνόδου . Στα πλαίσια της παρούσας διπλωματικής εργασίας παρουσιάζεται ένα σύστημα , υλοποιημένο σε FPGA , που προσομοιώνει έναν χρήστη SIP , κι έχει τη δυνατότητα να λαμβάνει , να επεξεργάζεται και να απαντά σε μηνύματα για την δημιουργία μια συνόδου . Στα κεφάλαια που ακολουθούν παρουσιάζεται η δομή του πρωτοκόλλου και τα χαρακτηριστικά του συστήματος που υλοποιήθηκε . Αρχικά παρουσιάζονται οι βασικές αρχές του πρωτοκόλλου και τα δομικά στοιχεία του . Έπειτα αναλύεται η δομή ενός SIP μηνύματος κι εξηγούνται οι λόγοι που κάνουν την αποθήκευσή του απαιτητική εργασία για την CPU . Έπειτα αναλύεται η βασική διαδικασία δημιουργίας συνόδου χρησιμοποιώντας ένα παράδειγμα . Το επόμενο μέρος αφιερώνεται στην αναλυτική περιγραφή του συστήματος που υλοποιήθηκε και την διαδικασία ελέγχου της ορθής λειτουργίας του . Τέλος παρουσιάζονται τα αποτελέσματα και συμπεράσματα της εργασίας . / The wide spread of networks based on Internet Protocol (IP), gave the opportunity for using the Internet for voice transmission , through Voice over IP (VoIP) technology, over traditional public telephone networks (PSTN). The Session Initiation Protocol is a signaling protocol , used to control multimedia sessions such as voice calls or video calls in IP networks. The use of this protocol in mobile devices , where resources management is very important ,is giving the stimulus for the creation of special hardware that offloads the CPU of demanding controls needed to create a session . As part of this thesis ,a system implemented on FPGA, which simulates a SIP user, and has the ability to receive, process and respond to messages to create a session , is presented. The following chapters present the structure of the protocol and the characteristics of the implemented system . Originally presented the basic principles of the Protocol and its structural elements . Thereafter the structure of a SIP message is analyzed , and the reasons that make storing a demanding work for the CPU , are explained. Then the basic process of creating a session is analyzed , using an example . The next part is devoted to a detailed description of the implemented system and the process of verifying the proper operation. Finally are presented the results and conclusions of the work .

Field-programmable gate arrays (FPGAs) have the potential to address scaling challenges in CMOS technology because of their regular structures and the flexibility they possess by being re-configurable after fabrication. One of the potential approaches in attacking scaling challenges, such as negative-bias temperature instability (NBTI) and process variation (PV), is by using placement techniques that are aware of these problems. Such techniques aim at placing a circuit in an FPGA such that the critical path delay is improved compared to the expected worst case. This can be achieved by placing NBTI-critical blocks of a circuit in areas with fast transistors in an FPGA chip. In this thesis, we present a detailed research effort that addresses the joint effect of NBTI and PV in FPGAs. We follow an experimental methodology in that we use actual PV data that we measure from 15 FPGA chips. The measured data is used to study the joint effect of NBTI and PV on the timing performance of circuits that are placed and routed in FPGAs. Enhancements are made to a well-known FPGA placement algorithm, T-VPlace, in order to make the placement process aware of the joint effect of NBTI and PV. Results are given for the placement and routing of Microelectronics Center of North Carolina (MCNC) benchmark circuits to show the effectiveness of the proposed techniques in addressing scaling challenges in FPGAs. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2009-09-24 17:23:29.626

The complexity of Field-Programmable Gate Array (FPGAs) logic blocks have undergone constant evolution to the point where both the basic soft logic blocks that implement combinational logic and the fixed-function hard blocks contain complex interconnects, hierarchy and modes. The goal of this thesis is to both support that complexity and enable future architecture exploration of even increased complexity and new kinds of hard functionality. To accomplish this, a Computer-Aided Design (CAD) flow that can map a user circuit to an FPGA with these complex blocks is needed. We propose a new language that can describe these complex blocks and a new area-driven tool for the packing stage of that CAD flow. The packing stage groups components of a user circuit into the complex blocks available on the FPGA. We conduct experiments to illustrate the quality of the packing tool and to demonstrate the newly-enabled architecture exploration capabilities.

A Field-Programmable Gate Array (FPGA) is a configurable platform for implementing a variety of logic circuits. It implements a circuit by the means of logic elements, usually Lookup Tables, connected by a programmable routing network. To utilize an FPGA effectively Computer Aided Design (CAD) tools have been developed. These tools implement circuits by using a traditional CAD flow, where the circuit is analyzed, synthesized, technology mapped, and finally placed and routed on the FPGA fabric. This flow, while generally effective, can produce sub-optimal results because once a stage of the flow is completed it is not revisited. This problem is addressed by an enhanced flow known Physical Synthesis, which consists of a set of iterations of the traditional flow with one key difference: the result of each iteration directly affects the result of the following iteration. An optimization can therefore be evaluated and then adjusted as needed in the following iterations, resulting in an overall better implementation. This CAD flow is challenging to work with because for a given FPGA researchers require access to each stage of the flow in an iterative fashion. This is particularly challenging when targeting modern commercial FPGAs, which are far more complex than a simple Lookup Table and Flip-Flop model generally used by the academic community. This dissertation describes a unified framework, called the Physical Synthesis Toolkit (PST), for research and development of optimizations for modern FPGA devices. PST provides access to modern FPGA devices and CAD tool flow to facilitate research. At the same time the amount of effort required to adapt the framework to a new FPGA device is kept to a minimum. To demonstrate that PST is an effective research platform, this dissertation describes optimization and modeling techniques that were implemented inside of it. The optimizations include: an area reduction technique for XOR-based logic circuits implemented on a 4-LUT based FPGA (25.3% area reduction), and a dynamic power reduction technique that reduces glitches in a circuit implemented on an Altera Stratix II FPGA (7% dynamic power reduction). The modeling technique is a novel toggle rate estimation approach based on the XOR-based decomposition, which reduces the estimate error by 37% as compared to the latest release of the Altera Quartus II CAD tool.

The complexity of Field-Programmable Gate Array (FPGAs) logic blocks have undergone constant evolution to the point where both the basic soft logic blocks that implement combinational logic and the fixed-function hard blocks contain complex interconnects, hierarchy and modes. The goal of this thesis is to both support that complexity and enable future architecture exploration of even increased complexity and new kinds of hard functionality. To accomplish this, a Computer-Aided Design (CAD) flow that can map a user circuit to an FPGA with these complex blocks is needed. We propose a new language that can describe these complex blocks and a new area-driven tool for the packing stage of that CAD flow. The packing stage groups components of a user circuit into the complex blocks available on the FPGA. We conduct experiments to illustrate the quality of the packing tool and to demonstrate the newly-enabled architecture exploration capabilities.

Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times during circuit operation, thereby reducing switching activity and lowering dynamic power. The concept is rooted in the property that under certain conditions, some signals within digital designs are not "observable" at design outputs, making the circuitry that generates such signals a candidate for guarding. Guarded evaluation has been demonstrated successfully for custom ASICs; in this work, we apply the technique to FPGAs. In ASICs, guarded evaluation entails adding additional hardware to the design, increasing silicon area and cost. Here, we apply the technique in a way that imposes minimal area overhead by leveraging existing unused circuitry within the FPGA. The LUT functionality is modified to incorporate the guards and reduce toggle rates. The primary challenge in guarded evaluation is in determining the specific conditions under which a sub-circuit's inputs can be held constant without impacting the larger circuit's functional correctness. We propose a simple solution to this problem based on discovering gating inputs using "non-inverting paths" and trimming inputs using "partial non-inverting paths" in the circuit's AND-Inverter graph representation. Experimental results show that guarded evaluation can reduce switching activity by as much as 32% for FPGAs with 6-LUT architectures and 25% for 4-LUT architectures, on average, and can reduce power consumption in the FPGA interconnect by 29% for 6-LUTs and 27% for 4-LUTs. A clustered architecture with four LUTs to a cluster and ten LUTs to a cluster produced the best power reduction results. We implement guarded evaluation at various stages of the FPGA CAD flow and analyze the reductions. We implement the algorithm as post technology mapping, post packing and post placement optimizations. Guarded Evaluation as a post technology mapping algorithm inserted the most number of guards and hence achieved the highest activity and interconnect reduction. However, guarding signals come with a cost of increased fanout and stress on routing resources. Packing and placement provides the algorithm with additional information of the circuit which is leveraged to insert high quality guards with minimal impact on routing. Experimental results show that post-packing and post-placement methods have comparable reductions to post-mapping with considerably lesser impact on the critical path delay and routability of the circuit.

In this thesis a microcontroller core is developed in an FPGA. Its instruction set is compatible with the microcontroller PIC16XX series by Microchip Technology. The microcontroller employs a RISC architecture with separate busses for instructions and data. Our goal in this research is to implement and evaluate the design in the FPGA. Increasing performance and gate capacity of recent FPGA devices permits complex logic systems to be implemented on a single programmable device. Such a growing complexity demands design approaches, which can lead to designs containing millions of logic gates, memories, high-speed interfaces, and other high-performance components. In recent years, the continuous development in the area of highly integrated circuits has lead to a change in the design methods used, making it possible to economically utilize FPGAs in many designs. A test demo board from the Digilent Inc is used to fit our testing requirements of the RISC microcontroller. The test demo board also had the capability of communicating with a personal computer (PC) so that we can load the program from PC. Based on the modern design methods the microcontroller core is developed using the Verilog hardware description language. Xilinx ISE Foundation 6.3i software is used for its synthesis and implementation. An embedded test program code using MPLAB is also developed, and then loaded into the designed microcontroller residing in the FPGA. In order to perform a functional test of the microcontroller core a special test program downloader application is designed by using Borland C++ Builder. First, the specification from the PIC16XX datasheet is transferred into an abstract behavioral description. Based on that, the next step is to develop a description of the microcontroller core with some minor modifications which can be synthesizable into a FPGA. Finally, the resulting gate level netlist is evaluated and tested using a demo board.