published_or_final_version / Electrical Engineering / Master / Master of Philosophy

The ability to numerically determine the received signal in an ultrasound pulse-echo system is very important for the development of new ultrasound applications, such as tissue characterization, complex object recognition, and identification of surface topology. The output signal from an ultrasound pulse-echo system depends on the transducer geometry, reflector shape, location and orientation, among others, therefore, only by numerical modeling can the output signal for a given measurement configuration be predicted. This thesis concerns about the numerical modeling and optimal design of annular array based ultrasound pulse-echo system for object recognition. Two numerical modeling methods have been implemented and evaluated for calculating received signal in a pulse-echo system. One is the simple, but computationally demanding Huygens Method and the other one is the computationally more efficient Diffraction Response for Extended Area Method (DREAM). The modeling concept is further extended for pulse-echo system with planar annular array. The optimal design of the ultrasound pulse-echo system is based on annular array transducer that gives us the flexibility to create a wide variety of insonifying fields and receiver characteristics. As the first step towards solving the optimization problem for general conditions, the problem of optimally identifying two specific reflectors is investigated. Two optimization methods, the straightforward, but computationally intensive Global Search Method and the efficient Waveform Alignment Method, have been investigated and compared.

"Abstract Conventional ultrasound imaging systems use array transducers for focusing and beam steering, to improve lateral resolution and permit real-time imaging. This thesis research investigates a different use of array transducers, where the acoustic field and the receiver characteristics are designed such that the energy of the output signal from targets of a specified geometry is maximized. The output signal is the sum of the received signals obtained using all the possible combinations of transducer array elements as transmitter and receiver. This work is based on annular array transducers, but is applicable for any array configuration. The first step is the development of software for the efficient modeling of the wave interaction between transmitted field and target, and between the transducer and receiver field. Using this software, we have calculated the received signal for each combination of an array element as transmitter and the same or another array element as receiver, leading to an N x N received signal matrix for an N element array transducer. A waveform optimization algorithm is then implemented for the purpose of determining the set of delays for the individual array elements, which maximizes the energy of the sum of the received signals. In one implementation of this algorithm, the received signal with the maximum energy is considered as a reference signal, and specific delays are applied to the other signals so that any two signals produce a maximum correlation. This leads to an N x N delay matrix, which, however, is not readily implemented in a practical real-time system, which uses all the elements in an array transducer simultaneously to customize acoustic fields. Hence, the values in this delay matrix are fed into a linear programming optimizer tool to obtain a set of delay values, which makes its implementation practical. The optimized set of delays thus obtained is used to maximize the energy of the received signal for a given transducer and target geometry and hence to enhance the reflectivity of that target. It is also important to check the robustness of the optimized set of delays obtained above, for a given target geometry. Robustness refers to the sensitivity of the optimization to variation in target geometry. This aspect is also evaluated as a part of this thesis work."

Based on a Ph.D. thesis in the Dept. of Electrical Engineering, 1965. / Bibliography: p. 67.

"MIT-3221-19." / Bibliography: p. 78-81. / Contract AT(30-1)-3221.

published_or_final_version / Electrical Engineering / Master / Master of Philosophy

No description available.

The Induction Linac System Experiment (ILSE) is a heavy-ion fusion (HIF) device that is being designed at Lawrence Berkeley Laboratory (LBL). The machine will be capable of accelerating 16 carbon ion beams, which are subsequently merged into 4 beams, to energies in the neighborhood of 10 MeV (10 million electron- volts). The purpose of the experiment will be to demonstrate the process of simultaneous acceleration and current amplification for a multiple beam accelerator configuration. If this process can be mastered, the beams produced by a machine such as ILSE would be used to implode and heat a deuterium-tritium (D-T) fuel pellet and produce a thermonuclear inertial confinement fusion (ICF) burn. This technology of achieving a fusion reaction using ion beams is referred to as Heavy-Ion Fusion (HIF) [1].

No description available.

Cellular and mobile communication markets, together with CMOS technology scaling, have made complex systems-on-chip integrated circuits (ICs) ubiquitous. Moving towards the internet of things that aims to extend this further requires ultra-low power and efficient radio communication that continues to take advantage of nanoscale CMOS processes. At the heart of this lie orthogonal challenges in both system and circuit architectures of current day technology. By enabling transceivers at center frequencies ranging in several tens of GHz, modern CMOS processes support bandwidths of up to several GHz. However, conventional narrowband architectures cannot directly translate or trade-off these speeds to lower power consumption. Pulse-radio UWB (PR-UWB), a fundamentally different system of communication enables this trade-off by bit-level duty-cycling i.e., power-gating and has emerged as an alternative to conventional narrowband systems to achieve better energy efficiency. However, system-level challenges in the implementation of transceiver synchronization and duty-cycling have remained an open challenge to realize the ultra-low power numbers that PR-UWB promises. Orthogonally, as CMOS scaling continues, approaching 28nm and 14nm in production digital processes, the key transistor characteristics have rapidly changed. Changes in supply voltage, intrinsic gain and switching speeds have rendered conventional analog circuit design techniques obsolete, since they do not scale well with the digital backend engines that dictate scaling. Consequently, circuit architectures that employ time-domain processing and leverage the faster switching speeds have become attractive. However, they are fundamentally limited by their inability to support linear domain-to-domain conversion and hence, have remained un-suited to high-performance applications. Addressing these requirements in different dimensions, two pulse-radio UWB receiver and a continuous-time filter silicon prototypes are presented in this work. The receiver prototypes focus on system level innovation while the filter serves as a demonstration vehicle for novel circuit architectures developed in this work. The PR-UWB receiver prototypes are implemented in a 65nm LP CMOS technology and are fully integrated solutions. The first receiver prototype is a compact UWB receiver front end operating at 4.85GHz that is aggressively duty-cycled. It occupies an active area of only 0.4 mm², thanks to the use of few inductors and RF G_m-C filters and incorporates an automatic-threshold-recovery-based demodulator for digitization. The prototype achieves a sensitivity of -88dBm at a data rate of 1Mbps (for a BER of 10^-3), while achieving the lowest energy consumption gradient (dP/df_data=450pJ/bit) amongst other receivers operating in the lower UWB band, for the same sensitivity. However, this prototype is limited by idle-time power consumption (e.g., bias) and lacks synchronization capability. A fully self-duty-cycled and synchronized UWB pulse-radio receiver SoC targeted at low-data-rate communication is presented as the second prototype. The proposed architecture builds on the automatic-threshold-recovery-based demodulator to achieve synchronization using an all-digital clock and data recovery loop. The SoC synchronizes with the incoming pulse stream from the transmitter and duty-cycles itself. The SoC prototype achieves a -79.5dBm, 1Mbps-normalized sensitivity for a >5X improvement over the state of the art in power consumption (375pJ/bit), thanks to aggressive signal path and bias circuit duty-cycling. The SoC is fully integrated to achieve RF-in to bit-out operation and can interface with off-chip, low speed digital components. Finally, switched-mode signal processing, a signal processing paradigm that enables the design of highly linear, power-efficient feedback amplifiers is presented. A 0.6V continuous-time filter prototype that demonstrates the advantages of this technique is presented in a 65nm GP CMOS process. The filter draws 26.2mW from the supply while operating at a full-scale that is 73% of the V_dd, a bandwidth of 70MHz and a peak signal-to-noise-and-distortion ratio (SNDR) of 55.8dB. This represents a 2-fold improvement in full-scale and a 10-fold improvement in the bandwidth over state-of-the-art filter implementations, while demonstrating excellent linearity and signal-to-noise ratio. To sum up, innovations spanning both system and circuit architectures that leverage the speeds of nanoscale CMOS processes to enable power-efficient solutions to next-generation wireless receivers are presented in this work.