Le transistor est la brique élémentaire des circuits intégrés présents dans tous les appareils électroniques. Années après années l’industrie de la microélectronique a amélioré les performances des circuits intégrés (rapidité, consommation énergétique) en réduisant les dimensions du transistor. De nos jours, en plus de la réduction de la taille du transistor d’autres techniques permettent de soutenir cette croissance: ce sont les « booster » technologiques. Les contraintes mécaniques ou encore le remplacement du Silicium par d’autres matériaux tels que germanium (Ge) et les matériaux semi-conducteurs de type III-V sont des exemples de booster technologiques. Grâce à la modélisation numérique, cette thèse propose d’étudier les effets de booster technologiques sur les performances électriques de la future génération de transistors. / The transistor is the elementary brick of Integrated circuits found in all electronic devices. Years after years the microelectronic industry has enhanced the performances of integrated circuits (speed and energy consumption) by downscaling the transistor. Nowadays besides the transistor’s downscaling, other techniques have been considered to maintain this growth: they are called technological boosters. Mechanical strain or new material, such as germanium (Ge) and III-V semiconductors, to replace Silicon are example of technological boosters. By the means of numerical quantum simulations and modeling, this these work propose a study of the effect of technological boosters on the electric performances of the next generation of transistors.

<div>With the transistor dimensions scaling down to a few atoms, quantum phenomena - like quantum tunneling and entanglement - will dictate the operation and performance of the next generation of electronic devices, post-CMOS era. While quantum tunneling limits the scaling of the conventional transistor, Tunneling Field Effect Transistor (TFET) employs band-to-band tunneling for the device operation. This mechanism can reduce the sub-threshold swing (S.S.) beyond the Boltzmann's limit, which is fundamentally limited to 60 mV/dec in a conventional Si-based metal-oxide-semiconductor field-effect transistor (MOSFET). A smaller S.S. ensures TFET operation at a lower supply voltage and, therefore, at lesser power compared to the conventional Si-based MOSFET.</div><div><br></div><div>However, the low transmission probability of the band-to-band tunneling mechanism limits the ON-current of a TFET. This can be improved by reducing the body thickness of the devices i.e., using 2-Dimensional (2D) materials or by utilizing heterojunction designs. In this thesis, two promising methods are proposed to increase the ON-current; one for the 2D material TFETs, and another for the III-V heterojunction TFETs.</div><div><br></div><div>Maximizing the ON-current in a 2D material TFET by determining an optimum channel thickness, using compact models, is presented. A compact model is derived from rigorous atomistic quantum transport simulations. A new doping profile is proposed for the III-V triple heterojunction TFET to achieve a high ON-current. The optimized ON-current is 325 uA/um at a supply voltage of 0.3 V. The device design is optimized by atomistic quantum transport simulations for a body thickness of 12 nm, which is experimentally feasible.</div><div> </div><div>However, increasing the device's body thickness increases the atomistic quantum transport simulation time. The simulation of a device with a body thickness of over 12 nm is computationally intensive. Therefore, approximate methods like the mode-space approach are employed to reduce the simulation time. In this thesis, the development of the mode-space approximation in modeling the triple heterojunction TFET is also documented.</div><div><br></div><div>In addition to the TFETs, quantum computing is an emerging field that utilizes quantum phenomena to facilitate information processing. An extra chapter is devoted to the electronic structure calculations of the Si:P delta-doped layer, using the empirical tight-binding method. The calculations agree with angle-resolved photoemission spectroscopy (ARPES) measurements. The Si:P delta-doped layer is extensively used as contacts in the Phosphorus donor-based quantum computing systems. Understanding its electronic structure paves the way towards the scaling of Phosphorus donor-based quantum computing devices in the future.</div>