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A wireless local area network (LAN) system is proposed to provide mobility for existing data communication services. This thesis presents a physical layer design for a direct sequence spread spectrum ISM band radio LAN system. This radio system employs spread spectrum communication technology and a differential binary phase shift keying/quadrature phase shift keying (BPSK/QPSK) non-coherent receiver to overcome the adverse indoor wireless environment. Moreover, a variable data rate transmission technique is used to dynamically configure the spread spectrum system according to channel performance. This physical layer incorporates the Zilog Z2000 Evaluation Board performing direct sequence spread spectrum processing, a Grayson 900 MHz radio receiver and a transmitter module which was designed and built at Virginia Tech. The transmitted spectrum occupies a 4 MHz bandwidth in the 900 MHz ISM band and this system supports a data rate of up to 363 Kbits/sec. The spread spectrum system design along with detailed descriptions of hardware and control software development are presented. / Master of Science

This project deals with possibilities of using the software defined radio conception for radio amateur use in a short wave band and its subsequent implementation into properly designed hardware. The aim of this work is to design a transceiver that would be capable of working in AM, FM, SSB, and CW modes. Within a theoretical part of the project the architectures of software defined radios and their components are discussed. This part was focused mainly on analog parts of the chain, such as amplifiers, filters and converters. Signal processing algorithms for both receiver and transmitter working in desired modes are studied subsequently and their computer models are built. Designed algorithms are implemented into FPGA structure (Virtex -5).

The radio frequency (RF) spectrum as a natural resource is severely under-utilized over time and space due to an inefficient licensing framework. As a result, in-creasing cellular and wireless network usage is placing significant demands on the licensed spectrum. This has led to the development of cognitive radios, software defined radios and mm-wave radios. Cognitive radios (CRs) enable more efficient spectrum usage over a wide range of frequencies and hence have emerged as an effective solution to handle huge network demands. They promise versatility, flex-ability and cognition which can revolutionize communications systems. However, they present greater challenges to the design of radio frequency (RF) front-ends. Instead of a narrow-band front-end optimized and tuned to the carrier frequency of interest, cognitive radios demand front-ends which are versatile, configurable, tun-able and capable of transmitting and receiving signals with different bandwidths and modulation schemes. The primary purpose of this thesis is to design a re-configurable, wide-band and low phase-noise fast settling frequency synthesizer for cognitive radio applications. Along with frequency generation, an area efficient multi-band low noise amplifier (LNA) with integrated built-in-self-test (BIST) and a strong immunity to interferers has also been proposed and implemented for these radios. This designed LNA relaxes the specification of harmonic content in the synthesizer output. Finally some preliminary work has also been done for mm-wave (V-band) frequency synthesis. The Key Contributions of this thesis are: A frequency synthesizer, based on a type-2, third-order Phase Locked Loop (PLL), covering a frequency range of 0.1-5.4 GHz, is implemented using a 0.13 µm CMOS technology. The PLL uses three voltage controlled oscillators (VCOs) to cover the whole range. It is capable of switching between any two frequencies in less than 3 µs and has phase noise values, compatible with most communication standards. The settling of the PLL in the desired state is achieved in dynamic multiple steps rather than traditional single step settling. This along with other circuit techniques like a DAC-based discriminator aided charge pump, fast acquisition pulse-clocked based PFD and timing synchro-negation is used to obtain a significantly reduced settling time A single voltage controlled LC-oscillator (LC-VCO) has been designed to cover a wide range of frequencies (2.0-4.1 GHz) using an area efficient and switch-able multi-tap inductor and a capacitor bank. The switching of the multi-tap inductor is done in the most optimal manner so as to get good phase-noise at the output. The multi-tap inductor provides a significant area advantage, and in spite of a degraded Q, provides an acceptable phase noise of -123 dBc/Hz and -113 dBc/Hz at an offset of 1 MHz at carrier frequencies of 2 and 4 GHz, respectively. Implemented in a 0.13 µm CMOS technology, the oscillator with ≈ 69 % tuning range, occupies an active area of only 0.095 mm2. An active inductor based noise-filter has been proposed to improve the phase-noise performance of the oscillator without much increase in the area. A variable gain multi-band low noise amplifier (LNA) is designed to operate over a wide range of frequencies (0.8 GHz to 2.4 GHz) using an area efficient switchable-π network. The LNA can be tuned to different gain and linearity combinations for different band settings. Depending upon the location of the interferers, a specific band can be selected to provide optimum gain and the best signal-to-intermodulation ratio. This is accomplished by the use of an on-chip Built-in-Self-Test (BIST) circuit. The maximum power gain of the amplifier is 19 dB with a return loss better than 10 dB for 7 mW of power consumption. The noise figure is 3.2 dB at 1 GHz and its third-order intercept point (I I P3) ranges from -15 dBm to 0 dBm. Implemented in a 0.13 µm CMOS technology, the LNA occupies an active area of about 0.29 mm2. Three different types of VCOs (stand-alone LC VCO, push-push VCO and a ring oscillator based VCO) for generating mm-wave frequencies have been implemented using 65-nm CMOS technology and their measured results have been analyzed