The field programmable gate array (FPGA) is an attractive computational platform for many applications because of its customizable nature and modest development cost, in terms of both time and money. As FPGAs scale to increased logical capacities, designers have increased flexibility. However, the FPGA placement problem becomes more difficult at increased sizes. Increasingly, designers are encouraged to structure designs hierarchically and floor-plan. Floor planning is a manual process which maps specified design submodules to selected physical regions of the FPGA device fabric. This thesis explores several of the effects that floor-planning has on submodules and the designs they comprise. A method is developed to explore the floor-planning impact on submodules independent of a full design. Six different submodules are independently subjected to varying timing constraints and to area constraints of varying aspect ratios and area allocations. The resulting submodule minimum clock periods, routing overflows, and relocatabilities are assembled from millions of submodule implementations. The aggregate results suggest that EDA placement and routing tools can meet design constraints even with extreme combinations of submodule aspect ratio and area allocations; however, the probability of implementations meeting constraints may be low at those extremes. Separate sets of submodule floor-planning guidelines are developed to optimize for meeting minimum clock period constraints, minimizing routing overflow, and maximize relocatability. The submodule floor planning guidelines for meeting minimum clock period are verified in full design implementations.