This work is concerned with the large class of nonlinear scalar field theories known as σ-models, and in particular with their classical solutions. It is shown how the σ-models can admit solitons in (2+1) dimensions; and how, in many cases, these solitons can be classified topologically. For the Kähler c-models, the instanton (i.e. static soliton) solutions are derived explicitly via the Bogomolny equations. The main part of the thesis looks at the behaviour of solitons under the influence of small perturbations, and at their (classical) interactions. Attention is confined to the O(3) a-model and its close relatives. A recurring theme is the ability of solitons to change in size as they evolve, a feature which is attributed to the conformal invariance of the theory. There seem to be three possible approaches. In some special cases, the theory is integrable, in the sense that one can write down explicit time-dependent solutions. More often, one must resort to a numerical simulation, or else some sort of approximation. For theories that possess a topological lower bound on the energy, there is a useful approximation in which the kinetic energy is assumed to remain small. All three of these approaches are used at various stages of the thesis. Chapter IIIdeals with the properties of wave-like solitons in an integrable theory, and reveals some hitherto unseen behaviour. Chapters IV and V develop a numerical simulation based on topological arguments, which is then used in a study of soliton stability in the pure O(3) model. The conclusion is that the solitons are unstable to small perturbations, in the sense that their size is subject to large changes, even though their energy remains roughly constant. Chapter VI uses the slow-motion approximation to investigate soliton interactions in the O(3) model, and uncovers a plethora of possibilities. Finally, some suggestions are made regarding possible directions for future research. In particular, attention is focussed on ways of modifying the O(3) model in an attemptto stabilize its solitons against changes in size

Thesis (Ph. D.)--University of Washington, 1998. / Vita. Includes bibliographical references (p. [85]-89).

No description available.

This thesis investigates the problem of optimal design of binary joint watermarking and scalar quantization (JWSQ) systems that are robust under additive Gaussian attacks. A binary JWSQ system consists of two quantizers with disjoint codebooks. The joint quantization and embedding are performed by choosing the quantizer corresponding to the embedded message. The optimal JWSQ design for both fixed-rate and variable-rate cases was considered in the past, but the solution approaches exhibited high computational complexity. In this thesis, we propose faster binary JWSQ design algorithms for both the fixed-rate and variable-rate scenarios. We achieve the speed up by mapping the corresponding optimization problem to a minimum weight path problem in a certain weighted directed acyclic graph (with a constraint on the length of the path in the fixed-rate case). For this mapping to be possible we discretize the quantizer space and use an approximation for the probability of decoding error. The proposed solution algorithms have $O(LN^3)$ and $O(N^4)$ time complexity in the two cases respectively, where $N$ is the size of discretized source alphabet, and in the fixed-rate scenario $L$ is the number of cells in each quantizer. The effectiveness of the proposed designs is assessed through extensive experiments on a Gaussian source. Our results show that our algorithms are able to achieve performance very close to the prior existing schemes, but only at a small fraction of their running time. / Thesis / Master of Applied Science (MASc)

No description available.

No description available.

No description available.

As a result of the microprocessor system research and the development of VLSI manufacturing process technology, the recent trend and development in high performance computer have toward to multi-core architecture. However current multi-core architectures are designed by the symmetric multi processors (SMP) concept. In traditional SMP mechanism, there are only data link between processor cores. So a single thread only can be handled by a single core, it limits the usage rate in multi-core and performance can not increase. This paper proposed a scalable chip multiprocessor architecture, which is called Hyper-scalar. The Principal characteristic of the architecture is ¡§design the interconnect control mechanisms for instructions in the multi-core¡¨. Some single scalar processor cores in Hyper-scalar architecture can be dynamically grouped as an n-way superscalar accelerator to improve the instruction-level parallelism, which is called accelerator group. Hyper-scalar combines the advantages of superscalar and multithreaded architecture; Hence, this architecture can not only enhance single-threaded performance by using accelerate group but also supports multithreaded applications. The paper based on ARM instruction set, to analyze how to create the interactive control mechanisms for instruction in the multi-core, and how to enhance the performance of a single thread in the Hyper-scalar architecture. It can be divided into four parts: register flow, memory flow, instruction control flow, chop of multi cycle instruction. When instructions are issued into the processor, they must be attached dependence tags that can solve the dependence between all issued instructions. All instructions can exchange the data through the virtual shared register file (VSRF) mechanism, and all instructions are executed only when the operands are available. In the memory flow part: we solve the dependence problem with a simple technique¡Xto execute instruction in instruction order. In instruction control flow part: in order to improve performance, we perform speculation execution mechanism, so the instructions can out of order execution beyond the basic block. Finally because there are some multi cycle instructions in the ARM instruction set, in hyper-scalar framework can chop into many one cycle instructions to further enhance performance. The simulation Model is written by SystemC, a modeling language based on C++ is to provide hardware-oriented simulation platform and the MediaBench suite is selected for the experiments. On average, the Hyper-scalar architecture can accelerate single-threaded performance by 50% to 300% using 2 ~ 8 cores.

No description available.

Thesis (M.Phil.)--Hong Kong University of Science and Technology, 2008. / Includes bibliographical references (leaves 55-57). Also available in electronic version.