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CHARACTERISTICS AND APPLICATIONS OF A SCANNING NANO-SLIT OPTICAL SENSORGeorge, Anoop January 2011 (has links)
In this dissertation, imaging characteristics of a nano-slit are investigated. Applications of a scanning and rotating nano-slit in measuring sub-micron aerial features are demonstrated. Coherent sub-micron spot distributions are reconstructed with a very high contrast. Finally, high NA partially coherent images with features as small as 210 nm half-pitch are reconstructed and the ultimate resolution of the system is determined.A nano-slit is characterized as a sensor for coherent line-and-space features. Experiments and simulation verify image detection with contrasts greater than 0.9. Effects of polarization on imaging performance are reported. A scanning and rotating nano-slit in conjunction with a filtered back-projection technique is used to reconstruct sub-micron coherent spot distributions. Simulation results show very good agreement with the experiment. Further, it is shown that the reconstruction is very resilient to some common random experimental errors.Imaging characteristics of a scanning nano-slit sensor are determined for high NA partially coherent images. Good imaging performance (contrast > 0.8) is demonstrated with line-and-space images up to a spatial frequency of 2.38 lp / micron. Sub-micron features in a high NA partially coherent image are measured with a scanning and rotating nano-slit. A modified microscope is used to create the measured features, including 210 nm half-pitch features that cannot be imaged using the microscope in a conventional imaging mode. Using the filtered back projection technique, two-dimensional sub-micron features are reconstructed by the nano-slit sensor. It is determined that the resolution limit of ~ 200 nm is determined by the reconstruction technique and not by the width of the nano-slit.
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Image interpolation in firmware for 3D displayWahlstedt, Martin January 2007 (has links)
<p>This thesis investigates possibilities to perform image interpolation on an FPGA instead of on a graphics card. The images will be used for 3D display on Setred AB’s screen and an implementation in firmware will hopefully give two major advantages over the existing rendering methods. First, an FPGA can handle big amounts of data and perform a lot of calculations in parallel. Secondly, the amount of data to transfer is drastically increased after the interpolation and with this, a higher bandwith is required to transfer the data at a high speed. By moving the interpolation as close to the projector as possible, the bandwidth requirements can be lowered. Both these points will hopefully be improved, giving a higher frame rate on the screen.</p><p>The thesis consists of three major parts, where the first handles methods to increase the resolution of images. Especially nearest neighbour, bilinear and bicubic interpolation is investigated. Bilinear interpolation was considered to give a good trade off between image quality and calculation cost and was therefore implemented. The second part discusses how a number of perspectives can be interpolated from one or a few captured images and the corresponding depth or disparity maps. Two methods were tested and one was chosen for a final implementation. The last part of the thesis handles Multi Video, a method that can be used to slice the perspectives into a form that is needed for the Scanning Slit display to show them correctly.</p><p>The quality of the images scaled with bilinear interpolation is satisfactory if the scale factor is kept reasonably low. The perspectives interpolated in the second part show good quality with lots of details but suffers from some empty areas. Further improvements of this function is not necessary but would increase the image quality further. An acceptable frame rate has been achieved but further improvements of the speed can be performed. The most important continuation of this thesis is to integrate the implemented parts with the existing firmware and with that enable a real test of the performance.</p>
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Image interpolation in firmware for 3D displayWahlstedt, Martin January 2007 (has links)
This thesis investigates possibilities to perform image interpolation on an FPGA instead of on a graphics card. The images will be used for 3D display on Setred AB’s screen and an implementation in firmware will hopefully give two major advantages over the existing rendering methods. First, an FPGA can handle big amounts of data and perform a lot of calculations in parallel. Secondly, the amount of data to transfer is drastically increased after the interpolation and with this, a higher bandwith is required to transfer the data at a high speed. By moving the interpolation as close to the projector as possible, the bandwidth requirements can be lowered. Both these points will hopefully be improved, giving a higher frame rate on the screen. The thesis consists of three major parts, where the first handles methods to increase the resolution of images. Especially nearest neighbour, bilinear and bicubic interpolation is investigated. Bilinear interpolation was considered to give a good trade off between image quality and calculation cost and was therefore implemented. The second part discusses how a number of perspectives can be interpolated from one or a few captured images and the corresponding depth or disparity maps. Two methods were tested and one was chosen for a final implementation. The last part of the thesis handles Multi Video, a method that can be used to slice the perspectives into a form that is needed for the Scanning Slit display to show them correctly. The quality of the images scaled with bilinear interpolation is satisfactory if the scale factor is kept reasonably low. The perspectives interpolated in the second part show good quality with lots of details but suffers from some empty areas. Further improvements of this function is not necessary but would increase the image quality further. An acceptable frame rate has been achieved but further improvements of the speed can be performed. The most important continuation of this thesis is to integrate the implemented parts with the existing firmware and with that enable a real test of the performance.
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