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No description available.

Semiconductor devices can be fabricated by growing III-V heteroepitaxial layers which are coherently strained to a III-V substrate. The relaxation of layer lattice strain through the nucleation of misfit dislocations near the interface causes a drop in performance for these devices. This thesis uses two non destructive x-ray techniques to examine relaxation in III-V epitaxial layers; double crystal diflractometry and x- ray topography. The dynamical and kinematical theories of x-ray diffraction are discussed in chapter 2. The apparatus used for double crystal diffractometry and x-ray topography and the theory of operation of these techniques is discussed in chapter 3. The properties of misfit dislocations in III-V epitaxial layers and the critical layer thickness at which relaxation occurs are discussed in chapter 4.Double crystal diffractometry and x-ray topography have been used to examine relaxation in epitaxial layers of AlAs on GaAs, InGaAs on GaAs, GaAsSb on GaAs, InGaAs on InP and an InGaAs superlattice on InP. All layers were deposited on 001 orientated substrates. Asymmetric double crystal rocking curves have been analysed using a novel technique which allows deduction of the position of an hhl layer reflection in reciprocal space. The layer unit cell parameters in the [110] and iTO] directions are determined from this. Individual misfit dislocation lines can be resolved by topography for dislocation line densities less than 0.2 μm(^-1)In each of these samples the layer relaxation was found to be asymmetric about the (110) directions. The sensitivity of diffractometry and topography to the detection of layer relaxation has been compared for samples with different thicknesses and dislocation line densities. The resolution of these techniques to the determination of layer relaxation has been shown to meet for a 1 μm layer of AlAs on GaAs. Tilt between the epitaxial layer lattice and the substrate has been measured for coherently strained and partially relaxed epitaxial layers grown on 001 orientated substrates. The lattice tilt in (110) directions was found to increase with misfit dislocation line density in these directions. Two theoretical models have been developed describing the relationship between lattice tilt and misfit dislocation line density and the tilts predicted by these compared with experiment. At high dislocation densities measurements of layer relaxation by diffractometry indicate that the images recorded by topography represent bundles of misfit dislocations and not individual dislocation fines. The number of dislocation lines per bundle was found to decrease with decreasing layer relaxation. Bunching of misfit dislocations into dislocation bundles is also observed on topographs from a low dislocation density sample where the individual dislocation hues are resolved. Screw dislocations in a strained layer and an interaction between two 60 dislocations to form a mixed dislocation have been characterised using Burgers vector analysis. Interference fringes have been observed on 004 double crystal rocking curves recorded from an ultra thin In GaAs layer sandwiched between a GaAs substrate and a GaAs cap. The position and intensity of these fringes was found to be sensitive to the composition and thickness of the In GaAs layer. Comparison between simulated and experimental rocking curve data allowed determination of the layer thickness to within a single monolayer and layer composition to within 0.5%. Topography of this sample showed that the dislocation line density varied from zero to 0.12 μm(^-1)across the wafer. The critical layer thickness and Indium concentration at which the first few misfit dislocation fines were observed was measured as 162 ± 2 A and 17 ± 0.5 %.

A new equivalent circuit model for IGBT is presented. It takes into account both electron and hole conduction in sensors and is incorporated with SPICE3 for the simulation of three types of current sensors, namely active, bipolar, and MOS sensors. It adopts a multi-MOS model to include the doping variation in the MOS body. The results agree well with the current sensing measurements within an average error of 4.4%.

The electrical characteristics of the Metal-Insulator-Semiconductor - Switch (MISS) device with Silicon-Rich-Oxide (SRO) as the semi-insulating material have been comprehensively studied at room temperature in an exploratory way. The SRO films were deposited by atmospheric pressure chemical vapour deposition (APCVD) at 650ºC with SiH(_4) and N(_2)O reactant gases and N(_2) carrier. The react ant gas phase ratio R(_o) varying from 0.09 to 0.25 and the deposition time varying from 0.6 to 2 min. Some preliminary investigations on SRO-MIS devices were also carried out in order to understand the electronic process in the structure. Various parameters which governed the switching behaviour of an MISS were investigated. In general the switching characteristics are similar to those of the tunnel oxide MISS. The geometrical dependence of the switching behaviour in the tunnel oxide MISS has been extended to the present device by looking at the effects of electrode area, junction area, electrode perimeters and of a metal guard ring. Other effects, such as SRO deposition time, work function difference, gold doping, heat treatment, light illumination and film ageing were also observed. The dynamic characteristic of the device was studied using a double pulse technique. The characteristics of the three-terminal SRO-MISS were studied in both forward and reverse bias. The former exhibited a thyristor-like characteristic and the latter a transistor-Hke characteristic. A preliminary study on the MIS-emitter transistor was carried out with different emitter areas. In general the characteristics are the same as for the equivalent tunnel oxide devices. However it was also found that if the n-type epilayer is very thin the transistor characteristics exhibits an N-type negative resistance. The negative resistance region of the two-terminal MISS has been shown to be stable and the stability has been analysed in terms of equivalent circuit elements. The reason for the stability is that the device also has an negative capacitance. This has been proved experimentally and it is a new property of the MISS structure which never been reported before. The negative capacitance has been measured as a function of electrode area, SRO type and light illumination. An important circuit application for the negative capacitance has also been suggested and demonstrated

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All semiconductor devices need electrical accessibility and thus some form of metal contact is required. This contact may be rectifying or ohmic, but the metals used in the chip construction are often unsuitable for making connections to the outside world. Invariably, layered metallizations are used to make the top metallic layer suitable for wire or tape ultrasonic-thermocompression bonding, usually involving aluminium or gold, or soldering using lead-tin alloys. When a semiconductor device is fabricated, it goes through a number of processes at the end of which it is metallized, passivated, encapsulated, and packaged, or any combination of these. The device engineer knows the structure of the device which will include a number of semiconductor-metal, insulator-metal, and metal-metal interfaces. In order to ascertain the operational reliability of the device, accelerated life-tests and predelivery burn-in or screening (or both) based on life tests are often carried out. This stressing involves operating the device either at high temperatures or at high current densities in normal atmospheric, corrosive or highly irradiated environments, or in environments consisting of combinations of these. The different interfaces in the device may change their characteristics through materials transferred by various means at the different stages mentioned above. The interfacial changes and any resultant alterations in the bulk of the constituting materials invariably alters the electrical or mechanical performances (or both) of the device which is said to have degraded. More importantly, operation of the device at high power levels or at high stressing causes thermal runaway and device failure. The work carried out and described in this thesis focuses on failures which occur in the connective paths, known as lines between individual device internal transistors. Firstly, the operation of the VLSI device in adverse elevated thermal and elevated current density conditions will be described. Whilst the process failure mechanisms under these conditions are well documented and mathematically defined, a new technique involving mechanical stress modelling has been developed to predict failures locations in the Al-Si 1% lines. Secondly, a new procedure has been developed to artificially 'age' VLSI devices in order to observe any degradation which may occur in the connecting paths. Several factors have been identified which can contribute to line degradation. These are high current density, high temperature and high mechanical stress. These factors together give rise to electromigration, resulting in the physical movement of line material, which eventually results in catastrophic line failure. It has been previously thought that only temperature and current density were the controlling factors, but this investigation has shown that mechanical stress has a major influence. A new model to predict electromigration phenomena locations in conductive paths has thus been developed based on mechanical stress, in addition to current density and surrounding temperature.

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No description available.

No description available.