In this thesis, a new design methodology for pipeline FFT processor has been proposed. The pipeline FFT processor can achieve high throughput rate, and is very suitable for those systems where the continuous data sequences that call for the FFT processing enter systems sample by sample sequentially. However, the traditional pipeline FFT design based on the common single delay feed-back approach suffers low hardware utilization for the butterfly unit. In addition, the resulted transformed sequence is in the form of bit-reverse order which is not suitable for some FFT applications such as OFDM (Orthogonal Frequency Division Multiplexing). Therefore, this thesis proposes a novel pipelined FFT design by first splitting the input sequence into two data streams, which can then be applied to the FFT data-path based on the feed-forward dual-delay path data commutator. The resulted FFT architecture can achieve full butterfly utilization such that the required number of adders can be reduced by almost a half. One potential drawback of the proposed approach is that some additional large storage buffer is required at the last stage. However, the additional storage buffer can be re-organized and merged with the output reordering buffer together such that the normal-order transformed output sequence can be generated. The proposed approach has been applied to the design of 8-K point FFT in this thesis. The 8-K FFT architecture proposed in this thesis is designed based on the radix- 2^4 algorithm such that the required number of general complex number multipliers can be minimized to three. The multiplication of is realized by the dedicated constant multiplier architecture. By proper data partition and allocation, the large buffer required for many data commutator and the output reordering buffer can both be efficiently realized by multi-bank single-port memory modules. The other salient features of the 8-K FFT also include the table reduction for twiddle factors as well as the optimized variable internal data representation. The proposed FFT processor has been implemented by the TSMC 0.18um 1P6M CMOS process technology with core area of 8.74 which is the smallest design reported in the literature for normal sequential input/output order FFT.