<p>This assignment has been given by Defence Communication (DC) which is a division of Kongsberg Defence and Aerospace(KDA). KDA develops amongst other things military radio equipment for communication and data transfer. In this equipment there is use of digital logic that performes amongst other things integer and fixed point division. Current systems developed at KDA uses both application specific integrated circuit (ASIC) and field programmable gate arrays (FPGA) to implement the digital logic. In both these technologies it is implemented circuit to performed integer and fixed point division. These are designed for low latency implementations. For future applications it is desire to investigate the possibility of implementing a high throughput pipelined division circuit for both 16 and 64 bit operands. In this project several commonly implemented division methods and algorithms has been studied, amongst others digit recurrence and multiplicative algorithms. Of the studied methods, multiplicative methods early stood out as the best implementation. These methods include the Goldschmidt and Newton-Raphson method. Both these methods require and initial approximation towards the correct answer. Based on this, several methods for finding an initial approximation were investigated, amongst others bipartite and multipartite lookup tables. Of the two multiplicative methods, Newton-Raphsons method proved to give the best implementation. This is due to the fact that it is possible with Newton-Raphsons method to implement each stage with the same bit widths as the precision out of that stage. This means that each stage is only halve the size of the succeeding stage. Also since the first stages were found to be small compared to the last stage, it was found that it is best to use a rough approximation towards the correct value and then use more stages to achieve the target precision. To evaluate how different design choices will affect the speed, size and throughput of an implementation, several configurations were implemented in VHDL and synthesized to FPGAs. These implementations were optimized for high speed whit high pipeline depth and size, and low speed with low pipeline depth and size. This was done for both 16 and 64 bits implementations. The synthesizes showed that there is possible to achieve great speed at the cost of increased size, or a small circuit while still achieving an acceptable speed. In addition it was found that it is optimal in a high throughput pipelined division circuit to use a less precise initial approximation and instead use more iterations stages.</p>

<p>A comparator-based switched capacitor integrator for use in a Delta Sigma ADC has been designed. Basic theory about comparator-based circuits has been presented and design equations have been developed. The integrator had a targeted performance of a bandwidth of 1.5MHz with a SNR of 80dB. Due to the lack of a complete modulator feedback system, the integrator was simulated in open-loop. For the integrator not to saturate in open-loop, an overshoot calibration circuit was enabled during the simulation. This resulted in a severe deterioration of the integrated signal. The results are therefore significantly lower than expected, with a SNR of about 39dB but can be expected to be better in a closed-loop simulation. The power consumption of the implemented modules is 0.43mW. However, this is without several modules which were implemented as ideal.</p>

<p>In this report I will look at the possibility of using a sensor network to control the interference to primary users made by secondary users. I'm going to use two Rayleigh fading channels, one to simulate the channel between the secondary transmitter and the sensor, and another to simulate the channel between the secondary transmitter and secondary receiver. I assume that the system is either using multiple antennas or that the secondary transmitter is moving relative to the sensor and primary user so that the channels share the same statistics. If the interference level gets too high at the sensor it should limit the transmission power at the secondary transmitter. And when it reaches a low level, the secondary transmitter can transmit with a higher power, depending on the channel between the two secondary users. I will study where the system stabilize. What the different variables control in the system. How the factor between the signal received at the sensor and the signal received at the secondary user are for different arrival rates. In the results i found out that small arrival rates have the highest efficiency compared to power at the secondary user and the sensor. When using a peak power constrain it helped stabilizing the system.</p>

<p>Energy efficiency in embedded processors is of major importance in order to achieve longer operating time for battery operated devices. In this thesis the energy efficiency of a microcontroller based on the open source ZPU microprocessor is evaluated and improved. The ZPU microprocessor is a zero-operand stack machine originally designed for small size FPGA implementation, but in this thesis the core is synthesized for implementation with a 180nm technology library. Power estimation of the design is done both before and after synthesis in the design flow, and it is shown that power estimates based on RTL simulations (before synthesis) are 35x faster to obtain than power estimates based on gate-level simulations (after synthesis). The RTL estimates deviate from the gate-level estimates by only 15% and can provide faster design cycle iterations without sacrificing too much accuracy. The energy consumption of the ZPU microcontroller is reduced by implementing clock gating in the ZPU core and also implementing a tiny stack cache to reduce stack activity energy consumption. The result of these improvements show a 46% reduction in average power consumption. The ZPU architecture is also compared to the more common MIPS architecture, and the Plasma CPU of MIPS architecture is synthesized and simulated to serve as comparison to the ZPU microcontroller. The results of the comparison with the MIPS architecture shows that the ZPU needs on average 15x as many cycles and 3x as many memory accesses to complete the benchmark programs as the MIPS does.</p>

<p>A high performance sound card is designed and implemented using a USB enabled microcontroller and an external dataconverter. Data is retrieved either via USB or S/PDIF. The sampling clock is generated by a precision clock synthesizer. This is programmable and can be adapted to different sampling rates of USB data. The system supports 24 bit, 192 kHz audio. Signal attenuation is performed through a relay based stepped voltage divider with constant output impedance. 64 dB attenuation in steps of 1 dB is available. An extensive power supply is made to support the range of required voltages. The signal to noise ratio of the power supply was measured to be 93 dB in the audio frequency band. The microcontroller has been programmed to handle the USB communication and provision of control signals for the system. The whole system is assembled on PCBs and tested. The audio performance measurements show a dynamic range of 105 dB, measured at the system output in a noisy environment. The total harmonic distortion plus noise was 0.0011 %.</p>

<p>In this study an underwater acoustic communications system has been simulated. The simulations has been performed through use of a simulation program called EasyPLR that is based on the PlaneRay propagation model. In the simulations different pulse shapes have been tested for use in underwater communication. Different types of loss have also been studied for different carrier frequencies. Changing the carrier frequency from 20 kHz to 75 kHz gives a huge difference in both absorption loss and reflection loss. This means that there will be a tradeoff between having a high frequency for high data rate and reducing the carrier frequency to reduce the loss. The modulation technique used in this study is Quadrature phase shift keying and different sound speed profiles have been tested to see how this affects the performance. The transmission distance has been tested for several distances up to 3 km. The results show a significant difference in the performances at 1 km and 3 km for the same noise level. Direct sequence spread spectrum with Quadrature phase shift keying has also been simulated for different distances with good performance. The challenge is to get good time synchronization, and the performance is much better at 1 km than at 3 km.</p>

<p>The classical front end analysis in speech recognition is a spectral analysis which parametrizes the speech signal into feature vectors; the most popular set of them is the Mel Frequency Cepstral Coefficients (MFCC). They are based on a standard power spectrum estimate which is first subjected to a log-based transform of the frequency axis (mel- frequency scale), and then decorrelated by using a modified discrete cosine transform. Following a focused introduction on speech production, perception and analysis, this paper gives a study of the implementation of a speech generative model; whereby the speech is synthesized and recovered back from its MFCC representations. The work has been developed into two steps: first, the computation of the MFCC vectors from the source speech files by using HTK Software; and second, the implementation of the generative model in itself, which, actually, represents the conversion chain from HTK-generated MFCC vectors to speech reconstruction. In order to know the goodness of the speech coding into feature vectors and to evaluate the generative model, the spectral distance between the original speech signal and the one produced from the MFCC vectors has been computed. For that, spectral models based on Linear Prediction Coding (LPC) analysis have been used. During the implementation of the generative model some results have been obtained in terms of the reconstruction of the spectral representation and the quality of the synthesized speech.</p>

<p>Cryptographic algorithms, like the Advanced Encryption Standard, are frequently used in todays electronic appliances. Battery operated devices are increasingly popular, creating a demand for low energy solutions. As a microcontroller is incorporated in virtually all electronic appliances, the main objective in this thesis is to evaluate possible hardware implementations of AES and implement a solution optimized for low energy consumption, suited for incorporation in a microcontroller. A good cost/performance balance is also a design goal. An existing solution based on a 32 bit architecture with support for 128 bit keys was chosen as a basis and altered in order to lower area and energy consumption. The alterations yielded a 13.6% area reduction as well as 14.2% and 3.9% reduction in energy consumption in encryption and decryption mode, respectively. In addition to alterations in the datapath, low energy techniques like clock gating and numerical strength reduction has been applied in order to further lower the energy consumption. The proposed architecture was also extended in order to accommodate 256 bit keys. Although this increased the area by 9.2%, the power consumption was still reduced by 7.6% and 1.3% in en- and decryption, compared to the architecture chosen as basis. As AES is an algorithm which easily can be parallelized, a high throughput solution utilizing a 128 bit datapath was implemented. This AES module is able to process 372.4 Mbps at an operating frequency of 32 Mhz and is based on the same architecture as the 32 bit datapath solution. In addition, this implementation yielded excellent energy per encryption figures, 24.5% lower than the 32 bit solution. The alternative to performing AES in a dedicated hardware module is to perform it using software. In order to have a basis for comparison, a software solution optimized for 32 bit architectures was implemented. Simulations show that the energy consumption attained when performing AES in the proposed hardware module is approximately 2.3% of what a software solution would use. In addition, the throughput is increased by a factor of 25. The architecture proposed in this thesis combines relatively high throughput with modest demands to area and low energy per encryption.</p>

<p>Lidar is an optical remote sensing technology which uses the backscattered light to create information profiles of the scanning area. Normally the air is used as propagation medium, but in this work the Lidar's efficiency to detect submerged target in water is discussed.   Following the theories of light propagation in the air and in the water a model to simulate the target detection is created. The values of scattering and absorption of the laser pulse in water are estimated by Morel equations which give accurate values of the sea water properties. Scattering and absorption define the optical properties of the medium, so the attenuation and the backscattering coefficient are calculated. These value will have a strong dependency to the salinity, pressure, temperature, sea water constituents and so on.   After the estimation of the parameters a model based on Lidar Equation, Fresnel Equations and Snell´s law has been developed with the aim of predict the maximum range to detect the sea surface and the maximum depth to detect the sea bottom.     In order to verify the goodness of the model, a prototype 532nm Lidar system has been used to collect experimental data. The Lidar was used from a 50m high building scanning from near vertical incidence to near horizontal incidence.   The extracted data from the simulations have been compared with the data obtained from realized test. This has given  us a predicted maximum range to detect the sea surface of 220m and an estimated  maximum depth for a reference target of 17m.</p>

<p>This report describes the assessment and design of a 10 dBm 2.4 GHz CMOS PA including driver stage. The PA is designed in a 0.18 um CMOS technology. A three stage PA has been designed due to the high voltage gain needed. Class F has been chosen for the output stage. An output filter short-circuiting the second harmonic frequency and reflecting the third harmonic frequency is used to obtain the near-square drain voltage that is characteristic to class F. A lowered supply voltage of 0.9 V is used to avoid exceeding the transistor break-down voltage of 2 V. The typical output power achieved is 10.2 dBm. The drain efficiency of the output stage is 47.7 %, and the PAE of the entire PA is 30.5 %. The final layout excluding bonding pads consumes an area of 0.66 mm2, including four internal inductors consuming a total of 0.59 mm2. The PAE obtained is higher than those of a selection of recently published PAs that are comparable in technology, frequency and output power.</p>