With today’s technology, digital signal processing plays a major role. It is used widely in many applications. Many applications require high resolution in measured data to achieve a perfect digital processing technology. The key to achieve high resolution in digital processing systems is analog-to-digital converters. In the market, there are many types ADC for different systems. Delta-sigma converters has high resolution and expected speed because it’s special structure. The signal-to-noise-and-distortion (SINAD) and total harmonic distortion (THD) are two important parameters for delta-sigma converters. The paper will describe the theory of parameters and test method.

International Telemetering Conference Proceedings / October 26-29, 1992 / Town and Country Hotel and Convention Center, San Diego, California / For research purposes on helicopter rotor acoustics a large data acquisition system called TEDAS (Transputer based Expandable Data Acquisition System) has been developed. The key features of this system are: unlimited expandability and sum data rate, local storage of data during operation, very simple analog anti aliasing filtering due to extensive digital filtering, and integrated computational power which scales with the number of channels. The sample rate is up to 50 kHz/channel, the resolution is 16 bit, 360 channels are realized now. TEDAS consists of blocks with 8 A/D converters which are controlled by one transputer T800. The size of the local memory is 4 Mbyte. Any number of blocks (IDAM = Intelligent Data Acquisition Module) can be combined to a complete system. Data preprocessing is done in parallel inside the IDAMs. As for 16 bit systems the analog antialiasing filtering becomes a dominant factor of the costs, delta sigma ADCs with oversampling and internal digital filtering are used. This produces an exact linear phase and a stop band rejection of -90 dB.

In present day, digital signal processing (DSP) is a popular technology and widely used in many fields. There have increasing number of applications that need high resolution converters. Therefore, analog-to-digital converters play a major role in DSP, and a well-performed ADC will enhance the performance of a certain system. Different types of ADCs are available for various functions. Delta-sigma  converters are famous for high resolution. Dynamic parameters can be used to judge the performance of an ADC, this paper will focus on the critical parameters of spectrum analysis, which contains Signal-to-Noise-and-Distortion Ratio (SINAD), Effective Number of Bits (ENOB) and Spurious-free Dynamic Range (SFDR). The theory and test method of these critical parameters are proposed in this paper using the Evaluation Module and Matlab. The results we acquired from the Evaluation Module are SINAD=86.15dB, SFDR=109.2dB, ENOB=14.177bits; and the results we calculated from MATLAB are: SINAD=86.14dB, SFDR=108.8dB, ENOB=14bits.

This dissertation presents a comprehensive design and analysis framework for system-on-a-chip analog-to-digital conversion design. The design encompasses a broad class of systems, which take advantage of system-on-a-chip complexity. This class is exemplified by an interferometric photodetector array based bio-optoelectronic sensor that is built and tested as part of the reported work. While there have been many discussions of the technical details of individual analog-to-digital converter (ADC) schemes in the literature, the importance of the analog front-end as a pre-processor for a data converter and the generalized analysis including converter encoding and decoding functions have not previously been investigated thoroughly, and these are key elements in the choice of converter designs for low-noise systems such as bio-optoelectronic sensors. Frequency domain analog front-end models of ADCs are developed to enable the architectural modeling of ADCs. The proposed models can be used for ADC statistically worst-case performance estimation, with stationary random process assumptions on input signals. These models prove able to reveal the architectural advantages of a specific analog-to-digital converter schemes quantitatively, allowing meaningful comparisons between converter designs. The modeling of analog-to-digital converters as communication channels and the ADC functional analysis as encoders and decoders are developed. This work shows that analog-to-digital converters can be categorized as either a decoder-centered design or an encoder-centered design. This perspective helps to show the advantages of nonlinear decoding schemes for oversampling noise-shaping data converters, and a new nonlinear decoding algorithm is suggested to explore the optimum solution of the decoding problem. A case study of decoder-centered and encoder-centered data converter designs is presented by applying the proposed theoretical framework. The robustness and flexibility of the resulting analog-to-digital converters are demonstrated and compared. The electrical and optical sensitivity measurements of a fabricated oversampling noise shaping analog-to-digital converter circuit are provided, and a sensor system-on-a-chip using these ADCs with integrated interferometric waveguides for bio-optoelectronic sensing is demonstrated.

The future voltage regulator module (VRM) challenges of high bandwidth control with fast transient response, high current output, simple implementation, and efficient 48V solution are tackled in this dissertation. With the push for control bandwidth to meet design specifications for microprocessor VRM with larger and faster load transients, control can be saturated and lost for a significant period of time during transient. During this time, undesirable transient responses such as large undershoot and ringback occurs. Due to the loss of control, the existing tools to study the dynamic behavior of the system, such as small signal model, are insufficient to analyze the behavior of the system during this time. In order to have a better understanding of the system dynamic performance, the operation the VRM is analyzed in the state-plane for a clear visual understanding of the steady-state and transient behaviors. Using the state-plane, a simplified state-plane trajectory control is proposed for constant on-time (COT) control to achieve the best transient possible for applications with adaptive voltage positioning (AVP). When the COT control is lost during a load step-up transient, the state-plane trajectory control will extend on-time to provide the a near optimal transient response. By observing the COT control law in the state-plane, a simplified state-plane trajectory control with analog implementation is proposed to achieve the best transient possible with smooth transitions in and out of the steady-state COT control. The concept of the simplified state-plane trajectory control is then extended to multiphase COT. For multiphase operation, additional operating behavior, such as phase overlapping during transient and interleaving during steady-state, need to be taken into consideration to design the desired state-plane trajectory control. A simple state-plane trajectory control with improved Ton extension is proposed and verified using multiphase COT control. After tackling the state-plane trajectory control for current mode COT, the idea is then extended to V2 COT. V2 COT is a more advanced current mode control which requires a more advanced state-plane trajectory control to COT. By calculating the intersection of the extended on-stage trajectory during transient and the ideal off trajectory in the form of a current limiting wall, a near optimal transient response can be achieved. For V2 COT with state-plane trajectory control, implementations using inductor vs. capacitor current, effect of component tolerance, and effect of IC delay are studied. The proposed state-plane trajectory control is then extended to enhanced V2 COT. Aside from tackling existing VRM challenges, the future datacenter 48V VRM challenge of a high efficiency, high power density solution to meet the VRM specifications is studied. The sigma converter is proposed for the 48V VRM solution due to exhibition of high efficiency and high-power density from hardware evaluation. An accurate model for the sigma converter is derived using the new modeling approach of modularizing the small signal components. Using the proposed model, the sigma converter is shown to naturally have very low output impedance, making the sigma converter suitable for microprocessor applications. The sigma converter is designed and optimized to achieve AVP and very fast transient response using both voltage-mode and current-mode controls. / Doctor of Philosophy / Microprocessors, such as central processing unit (CPU) and graphics processing unit (GPU) are the basis of today's electronics. In the recent decades, the demand for more powerful and faster data processing lead to a significant increase in power consumption by these microprocessors. Even with the introduction of multi-core processors and adaptive voltage positioning (AVP) to reduce the average power provided by the power supplies, the microprocessor can still draw a large amount of instantaneous power in a short period of time. With the microprocessors demanding high amount of current at fast slew-rate, the challenges for the next generation of microprocessor power supply, or voltage regulator modules (VRM), are fast response speed to ensure proper operation of the microprocessors, and high efficiency VRM to minimize the overall system power consumption. The challenge of a VRM with fast response speed is tackled first. To meet the AVP and transient requirements of microprocessor, the VR need to utilize high-bandwidth control methods. Of the control methods used by the industry, high control bandwidth can be easily achieved using constant on-time (COT) control. With the ever-increasing output current level and transient slew-rate requirements, COT control can saturate and lose its steady-state control for a period of time during load step-up transient. During this time, the system will operate with a fixed frequency control until COT control is recovered. Although the method is widely used in the industry, the method is too slow to meet the transient requirements. Many state-of-art methods have been proposed to resolve the load step-up transient issue of COT. However, of the methods proposed, it is difficult to optimize the transient improvement while having a simple analog implementation to ensure a fast response for the wide operating range and aggressive transient conditions observed in microprocessor VRM application. In this dissertation, COT control is studied using the state-plane to provide a clear visual understanding of the transient behavior of the control. Using the state-plane, a state-plane trajectory control is proposed to achieve near optimal load step-up transient response. The concept is then extended to multiphase VRM, which is typically used for high current applications. The state-plane trajectory control concept is then further extended to V2 COT control for VRM without AVP, such as those used by GPU and smartphone CPU. For the proposed state-plane trajectory controls, hardware implementation, evaluation, and experimental results are provided. After tackling the challenge of a VRM with fast response speed, the challenge of an efficient VRM is then tackled. In recent years, a significant amount of research has been put into studying VRM for a power delivery architecture which uses a 48V bus instead of the 12V bus. By using the 48V bus, less redundancy in the power delivery path can greatly increase the overall system efficiency if the VRM stage retains its efficiency. However, the increase in input voltage for the VRM provides an additional challenge to maintain high efficiency for the VRM stage itself. To maintain good efficiency, it is difficult to increase converter switching frequency beyond 300kHz. This limitation on switching frequency will limit the ability to achieve high bandwidth design and fast transient requirements. A 48V VRM using a different topology, the sigma converter, has demonstrated high-efficiency and high-power density, but the converter behavior and control methodology for VRM application is unclear. In this dissertation, the modeling and control of the sigma converter are studied using the proposed small-signal model. By evaluating the proposed small-signal model, the sigma converter can naturally have very low output impedance, making it an ideal candidate for 48V VRM. Then, the design guideline of the sigma converter with current-mode control is provided. With the work discussed in this dissertation, further study of the sigma converter with COT and state-plane trajectory control can be conducted in the future.