The ever advance of CMOS digital circuit process leads tothe trend of digitizing an analog signal and performing digitalsignal processing as early as possible in a signal processingsystem, which in turn leads to an increasing requirement onanalog- to-digital converter (ADC). A wireless transceiver is asuch kind of signal processing system. Conventionaltransceivers manipulate (filter, amplify and mix) the signalmostly in analog domain. Since analog filters are difficult todesign onchip, the system integration level is low. Moderntransceivers shift many of these tasks to digital domain, wherethe filtering and channel selection can be realized moreaccurately and more compactly. However the price for the highintegration level is the critical requirement on the ADC,because the simplified analog part sends not only the weaksignal but also the unwanted strong neighboring channel to theADC. In order to digitize the needed signal in the presence ofstrong disturbances, a high dynamic-range and high-speed ADC isneeded. Sigma Delta ADCs are promising candidates for A/D conversionin modern wireless transceivers. They are naturally suitablefor high-resolution narrow-band A/D conversions. With thedevelopment of processing and design techniques, sigma deltaADCs are expanding their applications to moderate-band area,such as wireless communication baseband processing. Currentlymobile communication systems are migrating from 2G to 3G. In 2Gsystems the baseband width is in the order of hundred kHz,while in 3G systems the baseband width is in the order of MHz.To face the challenge of designing a high resolution sigmadelta ADC with large bandwidth, a multi-bit internal quantizeris often used. In this thesis special design considerations onmulti-bit sigma delta modulators are discussed. The biggestdrawback of multi-bit sigma delta modulators isthe need of anextra circuit to attenuate or compensate the internal multi-bitDAC non-linearity. This thesis provides a comprehensiveanalysis of the solution which combines a multi-bit quantizerwith a 1-bit DAC in a sigma delta modulator. The theoreticalanalysis result is verified by measurement results. Anothertopic addressed in the thesis is how to reduce the multi-bitquantizer complexity. It is shown that by using a semiuniformquantizer, the quantizer can reduce its complexity by one-bityet still maintain the same modulator dynamic range. Theperformance of the semi-uniform quantizer is also verified bymeasurement results.

<p>The ever advance of CMOS digital circuit process leads tothe trend of digitizing an analog signal and performing digitalsignal processing as early as possible in a signal processingsystem, which in turn leads to an increasing requirement onanalog- to-digital converter (ADC). A wireless transceiver is asuch kind of signal processing system. Conventionaltransceivers manipulate (filter, amplify and mix) the signalmostly in analog domain. Since analog filters are difficult todesign onchip, the system integration level is low. Moderntransceivers shift many of these tasks to digital domain, wherethe filtering and channel selection can be realized moreaccurately and more compactly. However the price for the highintegration level is the critical requirement on the ADC,because the simplified analog part sends not only the weaksignal but also the unwanted strong neighboring channel to theADC. In order to digitize the needed signal in the presence ofstrong disturbances, a high dynamic-range and high-speed ADC isneeded.</p><p>Sigma Delta ADCs are promising candidates for A/D conversionin modern wireless transceivers. They are naturally suitablefor high-resolution narrow-band A/D conversions. With thedevelopment of processing and design techniques, sigma deltaADCs are expanding their applications to moderate-band area,such as wireless communication baseband processing. Currentlymobile communication systems are migrating from 2G to 3G. In 2Gsystems the baseband width is in the order of hundred kHz,while in 3G systems the baseband width is in the order of MHz.To face the challenge of designing a high resolution sigmadelta ADC with large bandwidth, a multi-bit internal quantizeris often used. In this thesis special design considerations onmulti-bit sigma delta modulators are discussed. The biggestdrawback of multi-bit sigma delta modulators isthe need of anextra circuit to attenuate or compensate the internal multi-bitDAC non-linearity. This thesis provides a comprehensiveanalysis of the solution which combines a multi-bit quantizerwith a 1-bit DAC in a sigma delta modulator. The theoreticalanalysis result is verified by measurement results. Anothertopic addressed in the thesis is how to reduce the multi-bitquantizer complexity. It is shown that by using a semiuniformquantizer, the quantizer can reduce its complexity by one-bityet still maintain the same modulator dynamic range. Theperformance of the semi-uniform quantizer is also verified bymeasurement results.</p>