In this dissertation, two high-frequency (HF) transformer isolated single-stage integrated ac-dc converters are proposed for a small scale permanent magnet synchronous generator (PMSG) based wind energy conversion system (WECS). These two types of single-stage integrated ac-dc converters include expected functions of HF isolation, power factor correction (PFC), and output regulation in one single-stage. Fixed-frequency phase-shift control and soft-switching operation are employed in both proposed ac-dc converters. After reviewing the literature and discussing pros and cons of the existing topologies, it is preferred that three identical single-phase single-stage integrated converters with interleaved connection configuration are suitable for the PMSG. For the single-phase converter, two new HF isolated single-stage integrated resonant ac-dc converters with fixed-frequency phase-shift control are proposed. The first proposed circuit is HF isolated single-stage integrated secondary-side controlled ac-dc converter. The other proposed circuit is HF isolated single-stage dual-tank LCL-type series resonant ac-dc converter, which brings better solutions compared to the first converter, such as high power factor and low total harmonic distortion (THD) at the ac input side. Approximate analysis approach and Fourier series methods are used to analyze these two proposed converters. Design examples for each one are given and designed converters are simulated using PSIM simulation package. Two experimental circuits are also built to verify the analysis and simulation. The simulated and experimental results reasonably match the theoretical analysis. Then the proposed HF isolated dual-tank LCL-type series resonant ac-dc converter is used for three-phase interleaved connection in order to satisfy requirements of PMSG based WECS. A design example for this three-phase interleaved configuration is given and simulated for validation under several operating conditions. / Graduate / 0544 / duyimian@uvic.ca

With the increasing demand for fast, cheaper, and efficient power converters come the need for a single-stage power factor correction (PFC) converter. Various single-stage PFC converter proposed in the literature has the drawback of high DC bus voltage at the input side and together with the shift to wide bandgap switches like GaN drives the converter cost higher. However, an interleaved topology with high-frequency isolation was proposed in this research work due to the drastic reduction in the DC bus voltage and extremely low input current ripple thereby making the need for an EMI filter circuit optional.   Meanwhile, this research work focuses on adapting the proposed topology for a high voltage low current application (EV charger - 400V, 7KW) and low voltage high current application (telecom power supply - 58V,  58A) owing to cost benefits. However, all single-stage PFC are faced with the drawback of second-order (100Hz) output harmonic ripple. Therefore, the design and simulation presented a huge peak to peak ripple of about 50V/3A and 26V/26A for the EV charger and telecom power supply case, respectively. This created the need for the design of a ripple cancellation circuit as the research required a peak to peak ripple of 8V and 200mV for the EV - charger and telecom power supply, respectively.   A novel output passive ripple cancellation technique was developed for the EV charger case due to the ease it offers in terms of control, circuit complexity and extremely low THDi when compared with the active cancellation approach. The ripple circuit reduced the 50V ripple to 431mV with the use of a total of 2.2mF capacitance at the output stage.   Despite designing the passive technique, an active ripple cancellation circuit was designed using a buck converter circuit for the telecom power supply. The active approach was chosen because the passive has a slow response and incurs more loss at a high current level. Adding the active ripple cancellation circuit led to a quasi-single stage LLC PFC converter topology. A novel duty-ratio feedforward control was added to synchronize the PFC control of the input side with the buck topology ripple cancellation circuit. The addition of the ripple circuit with the feedforward control offered a peak to peak ripple of 6.7mV and a reduced resonant inductor current by half.   After analysis, an extremely low THDi of 0.47%, PF of 99.99% and a peak efficiency of 97.1% was obtained for the EV charger case. The telecom power supply offered a THDi of 2.3%, PF of 99.96% with a peak efficiency of 95%.